{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,29]],"date-time":"2025-12-29T22:18:14Z","timestamp":1767046694463,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2010,11,1]],"date-time":"2010-11-01T00:00:00Z","timestamp":1288569600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2010,11]]},"abstract":"<jats:p>\n            Many techniques for power reduction in advanced RTL synthesis tools rely explicitly or implicitly on observability don\u2019t-care conditions. In this article we propose a systematic approach to maximize the effectiveness of these techniques by generating power-friendly RTL descriptions in behavioral synthesis. This is done using\n            <jats:italic>operation gating<\/jats:italic>\n            , that is, explicitly adding a predicate to an operation based on its observability condition, so that the operation, once identified as unobservable at runtime, can be avoided using RTL power optimization techniques such as clock gating.\n          <\/jats:p>\n          <jats:p>We first introduce the concept of behavior-level observability and its approximations in the context of behavioral synthesis. We then propose an efficient procedure to compute an approximated behavior-level observability of every operation in a dataflow graph. Unlike previous techniques which work at the bit level in Boolean networks, our method is able to perform analysis at the word level, and thus avoids most computation effort with a reasonable approximation. Our algorithm exploits the observability-masking nature of some Boolean operations, as well as the select operation, and allows certain forms of other knowledge to be considered for stronger observability conditions. The approximation is proved exact for (acyclic) dataflow graphs when non-Boolean operations other than select are treated as black boxes. The behavior-level observability condition obtained by our analysis can be used to guide the operation scheduler to optimize the efficiency of operation gating. In a set of experiments on real-world designs, our method achieves an average of 33.9% reduction in total power; it outperforms a previous method by 17.1% on average and gives close-to-optimal solutions on several designs. To the best of our knowledge, this is the first time behavior-level observability analysis and optimization are performed during behavioral synthesis in a systematic manner. We believe that our idea can be applied to compiler transformations in general.<\/jats:p>","DOI":"10.1145\/1870109.1870113","type":"journal-article","created":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T20:18:10Z","timestamp":1291234690000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis"],"prefix":"10.1145","volume":"16","author":[{"given":"Jason","family":"Cong","sequence":"first","affiliation":[{"name":"University of California, Los Angeles"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bin","family":"Liu","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rupak","family":"Majumdar","sequence":"additional","affiliation":[{"name":"University of California, Los Angeles"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhiru","family":"Zhang","sequence":"additional","affiliation":[{"name":"AutoESL Design Technologies, Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300997"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839489(410) 24"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.503933"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/323480.323482"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/258915.258930"},{"volume-title":"Proceedings of the Design, Automation and Test in Europe. 1016--1020","author":"Chen C.","key":"e_1_2_1_6_1"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147025"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233648"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594266"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687410"},{"volume-title":"Synthesis and Optimization of Digital Circuits","author":"De Micheli G.","key":"e_1_2_1_11_1"},{"key":"e_1_2_1_12_1","unstructured":"Devadas S. Ghosh A. and Keutzer K. 1994. Logic Synthesis. McGraw-Hill Inc. Devadas S. Ghosh A. and Keutzer K. 1994. Logic Synthesis. McGraw-Hill Inc."},{"key":"e_1_2_1_13_1","doi-asserted-by":"crossref","unstructured":"Forrest J. de la Nuez D. and Lougee-Heimer R. 2004. CLP user guide. http:\/\/projects.coin-or.org\/Clp. Forrest J. de la Nuez D. and Lougee-Heimer R. 2004. CLP user guide. http:\/\/projects.coin-or.org\/Clp.","DOI":"10.1287\/educ.1053.0020"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391638"},{"volume-title":"-L","year":"1992","author":"Gajski D. D.","key":"e_1_2_1_15_1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358036"},{"key":"e_1_2_1_17_1","doi-asserted-by":"crossref","unstructured":"Hassoun S. and Sasao T. 2002. Logic Synthesis and Verification. Springer. Hassoun S. and Sasao T. 2002. Logic Synthesis and Verification. Springer.","DOI":"10.1007\/978-1-4615-0817-5"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/356819.356822"},{"volume-title":"Proceedings of the International Symposium on Microarchitecture. 45--54","author":"Mahlke S. A.","key":"e_1_2_1_19_1"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240584"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343873"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/263272.263307"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.31522"},{"volume-title":"Proceedings of the 5th Workshop on EPIC Architecture and Compiler Technology.","author":"Ryoo S.","key":"e_1_2_1_24_1"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009866"},{"key":"e_1_2_1_26_1","unstructured":"Zhang Z. Fan Y. Jiang W. Han G. Yang C. and Cong J. 2008. High-Level Synthesis: From Algorithm to Digital Circuit. Springer Publishers Chapter AutoPilot: A platform-based ESL synthesis system. Zhang Z. Fan Y. Jiang W. Han G. Yang C. and Cong J. 2008. High-Level Synthesis: From Algorithm to Digital Circuit . Springer Publishers Chapter AutoPilot: A platform-based ESL synthesis system."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1870109.1870113","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1870109.1870113","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:59:47Z","timestamp":1750244387000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1870109.1870113"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11]]},"references-count":26,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2010,11]]}},"alternative-id":["10.1145\/1870109.1870113"],"URL":"https:\/\/doi.org\/10.1145\/1870109.1870113","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2010,11]]},"assertion":[{"value":"2010-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-11-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}