{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:31:31Z","timestamp":1750307491281,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,10,24]],"date-time":"2010-10-24T00:00:00Z","timestamp":1287878400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["644070"],"award-info":[{"award-number":["644070"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,10,24]]},"DOI":"10.1145\/1873548.1873553","type":"proceedings-article","created":{"date-parts":[[2010,11,1]],"date-time":"2010-11-01T13:32:23Z","timestamp":1288618343000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A comprehensive analysis of performance and side-channel-leakage of AES SBOX implementations in embedded software"],"prefix":"10.1145","author":[{"given":"Ambuj","family":"Sinha","sequence":"first","affiliation":[{"name":"Virginia Tech"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhimin","family":"Chen","sequence":"additional","affiliation":[{"name":"Virginia Tech"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Patrick","family":"Schaumont","sequence":"additional","affiliation":[{"name":"Virginia Tech"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,10,24]]},"reference":[{"unstructured":"Side-channel Attack Standard Evaluation Board. http:\/\/www.rcis.aist.go.jp\/special\/SASEBO\/SASEBO-G-en.html.  Side-channel Attack Standard Evaluation Board. http:\/\/www.rcis.aist.go.jp\/special\/SASEBO\/SASEBO-G-en.html.","key":"e_1_3_2_1_1_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1007\/978-3-540-89754-5_25"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_3_1","DOI":"10.5555\/647932.757246"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-662-04722-4","volume-title":"The Design of Rijndael","author":"Daemen J.","year":"2002","unstructured":"J. Daemen and V. Rijmen . The Design of Rijndael . Springer-Verlag New York, Inc. , Secaucus, NJ, USA , 2002 . J. Daemen and V. Rijmen. The Design of Rijndael. Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2002."},{"unstructured":"Digilent Inc. Spartan 3E-1600 Development Board. http:\/\/digilentinc.com\/Products\/Detail.cfm?NavPath=2 400 793&amp;Prod=S3E1600.  Digilent Inc. Spartan 3E-1600 Development Board. http:\/\/digilentinc.com\/Products\/Detail.cfm?NavPath=2 400 793&amp;Prod=S3E1600.","key":"e_1_3_2_1_6_1"},{"key":"e_1_3_2_1_7_1","volume-title":"The LEON3 Multiprocessing CPU Core. Product Sheet","author":"Gaisler A.","year":"2010","unstructured":"A. Gaisler . The LEON3 Multiprocessing CPU Core. Product Sheet , 2010 . http:\/\/www.gaisler.com\/doc\/leon3_product_sheet.pdf. A. Gaisler. The LEON3 Multiprocessing CPU Core. Product Sheet, 2010. http:\/\/www.gaisler.com\/doc\/leon3_product_sheet.pdf."},{"key":"e_1_3_2_1_8_1","volume-title":"Intel 64 and IA-32 Architectures Optimization Reference Manual","author":"Intel Inc.","year":"2007","unstructured":"Intel Inc. Intel 64 and IA-32 Architectures Optimization Reference Manual . 2007 . http:\/\/www.intel.com\/design\/processor\/manuals\/248966.pdf. Intel Inc. Intel 64 and IA-32 Architectures Optimization Reference Manual. 2007. http:\/\/www.intel.com\/design\/processor\/manuals\/248966.pdf."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1007\/978-3-642-04138-9_1"},{"doi-asserted-by":"crossref","unstructured":"P. C.\n      Kocher J.\n      Jaffe and \n      B.\n      Jun\n  . \n  Differential Power Analysis\n  . In M. J. Wiener editor CRYPTO volume \n  1666\n   of \n  Lecture Notes in Computer Science pages \n  388\n  --\n  397\n  . \n  Springer 1999\n  .   P. C. Kocher J. Jaffe and B. Jun. Differential Power Analysis. In M. J. Wiener editor CRYPTO volume 1666 of Lecture Notes in Computer Science pages 388--397. Springer 1999.","key":"e_1_3_2_1_10_1","DOI":"10.1007\/3-540-48405-1_25"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_11_1","DOI":"10.5555\/1791688.1791705"},{"key":"e_1_3_2_1_12_1","volume-title":"Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)","author":"Mangard S.","year":"2007","unstructured":"S. Mangard , E. Oswald , and T. Popp . Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security) . Springer-Verlag New York, Inc. , Secaucus, NJ, USA , 2007 . S. Mangard, E. Oswald, and T. Popp. Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security). Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2007."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_13_1","DOI":"10.1007\/11799313_22"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1007\/978-3-540-74735-2_9"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1007\/11605805_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1007\/11935070_14"},{"volume-title":"Data Sheet","year":"2010","unstructured":"Xilinx. Virtex-II Pro Platform FPGAs: Module 2: Functional Description . Data Sheet , 2010 . http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds083.pdf. Xilinx. Virtex-II Pro Platform FPGAs: Module 2: Functional Description. Data Sheet, 2010. http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds083.pdf.","key":"e_1_3_2_1_17_1"}],"event":{"sponsor":["CEDA Council on Electronic Design Automation","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"],"acronym":"ESWeek '10","name":"ESWeek '10: Sixth Embedded Systems Week","location":"Scottsdale Arizona"},"container-title":["Proceedings of the 5th Workshop on Embedded Systems Security"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1873548.1873553","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1873548.1873553","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:17:33Z","timestamp":1750249053000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1873548.1873553"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10,24]]},"references-count":17,"alternative-id":["10.1145\/1873548.1873553","10.1145\/1873548"],"URL":"https:\/\/doi.org\/10.1145\/1873548.1873553","relation":{},"subject":[],"published":{"date-parts":[[2010,10,24]]},"assertion":[{"value":"2010-10-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}