{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T18:53:39Z","timestamp":1777661619496,"version":"3.51.4"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T00:00:00Z","timestamp":1291161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2010,12]]},"abstract":"<jats:p>Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set\/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.<\/jats:p>","DOI":"10.1145\/1877745.1877748","type":"journal-article","created":{"date-parts":[[2010,12,22]],"date-time":"2010-12-22T14:41:31Z","timestamp":1293028891000},"page":"1-31","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":144,"title":["Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs"],"prefix":"10.1145","volume":"6","author":[{"given":"Himanshu","family":"Thapliyal","sequence":"first","affiliation":[{"name":"University of South Florida, Tampa, Tampa, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nagarajan","family":"Ranganathan","sequence":"additional","affiliation":[{"name":"University of South Florida, Tampa, Tampa, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,12,21]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Banerjee A. and Pathak A. 2007. On the synthesis of sequential reversible circuit. arXiv\/0707.4233.  Banerjee A. and Pathak A. 2007. On the synthesis of sequential reversible circuit. arXiv\/0707.4233."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2008.04.003"},{"key":"e_1_2_1_3_1","volume-title":"Proc. IEEE Symposium on VLSI. 83--88","author":"Bruce J. W."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.176.0525"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1324177.1324181"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2005.9"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1062261.1062324"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01857727"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2017215"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2008.42"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.871622"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxm042"},{"key":"e_1_2_1_13_1","first-page":"974","article-title":"Design of a novel reversible multiplier circuit using hng gate in nanotechnology","volume":"3","author":"Haghparast M.","year":"2008","journal-title":"World App. Sci. J."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.858352"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the International Conference on Computer and Information Technology. 515--519","author":"Khan M.","year":"2002"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1038\/35051009"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.53.0183"},{"key":"e_1_2_1_18_1","volume-title":"Digital Design","author":"Mano M. M."},{"key":"e_1_2_1_19_1","unstructured":"Maslov D. 2009. Reversible logic benchmarks http:\/\/webhome.cs.uvic.ca\/~dmaslov\/.  Maslov D. 2009. Reversible logic benchmarks http:\/\/webhome.cs.uvic.ca\/~dmaslov\/."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.836735"},{"key":"e_1_2_1_21_1","unstructured":"Maslov D. and Miller D. M. 2006. Comparison of the cost metrics for reversible and quantum logic synthesis. http:\/\/arxiv.org\/abs\/quant-ph\/0511008.  Maslov D. and Miller D. M. 2006. Comparison of the cost metrics for reversible and quantum logic synthesis. http:\/\/arxiv.org\/abs\/quant-ph\/0511008."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11128-009-0106-0"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.tcs.2008.01.041"},{"key":"e_1_2_1_24_1","unstructured":"Nielsen M. A. and Chuang I. L. 2000. Quantum Computation and Quantum Information. Cambridge Univ. Press Cambridge UK.   Nielsen M. A. and Chuang I. L. 2000. Quantum Computation and Quantum Information. Cambridge Univ. Press Cambridge UK."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.32.3266"},{"key":"e_1_2_1_26_1","first-page":"241","article-title":"Multi-valued sequential logic design using fredkin gates","volume":"1","author":"Picton P.","year":"1996","journal-title":"MVL J."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1692817"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxm116"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811448"},{"key":"e_1_2_1_30_1","volume-title":"Proceedings of the 49th IEEE International Midwest Symposism on Circuits and Systems., 437--441","author":"Sastry S. K."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.53.2855"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-00212-0_6"},{"key":"e_1_2_1_33_1","volume-title":"Proceedings of the International Conference on the Military and Aerospace Programmable Logic Devices.","author":"Thapliyal H."},{"key":"e_1_2_1_34_1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems. 625--628","author":"Thapliyal H."},{"key":"e_1_2_1_35_1","volume-title":"Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems. 342--346","author":"Thapliyal H."},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2007.12.006"},{"key":"e_1_2_1_37_1","doi-asserted-by":"crossref","unstructured":"Toffoli T. 1980. Reversible computing. Tech. rep. Tech memo MIT\/LCS\/TM-151 MIT Lab for Computer Science.  Toffoli T. 1980. Reversible computing. Tech. rep. Tech memo MIT\/LCS\/TM-151 MIT Lab for Computer Science.","DOI":"10.21236\/ADA082021"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.54.147"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1007\/11556930_22"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5042-2"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1877745.1877748","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1877745.1877748","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:47Z","timestamp":1750243967000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1877745.1877748"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":40,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2010,12]]}},"alternative-id":["10.1145\/1877745.1877748"],"URL":"https:\/\/doi.org\/10.1145\/1877745.1877748","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,12]]},"assertion":[{"value":"2009-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-12-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}