{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:31:22Z","timestamp":1750307482241,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,10,24]],"date-time":"2010-10-24T00:00:00Z","timestamp":1287878400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,10,24]]},"DOI":"10.1145\/1878921.1878933","type":"proceedings-article","created":{"date-parts":[[2010,11,9]],"date-time":"2010-11-09T15:01:31Z","timestamp":1289314891000},"page":"57-66","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Implementing virtual secure circuit using a custom-instruction approach"],"prefix":"10.1145","author":[{"given":"Zhimin","family":"Chen","sequence":"first","affiliation":[{"name":"Virginia Tech, Blacksburg, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ambuj","family":"Sinha","sequence":"additional","affiliation":[{"name":"Virginia Tech, Blacksburg, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Patrick","family":"Schaumont","sequence":"additional","affiliation":[{"name":"Virginia Tech, Blacksburg, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,10,24]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Aeroflex Gaisler. LEON3 Multiprocessing CPU Core. available at http:\/\/www.gaisler.com\/doc\/leon3_product_sheet.pdf.  Aeroflex Gaisler. LEON3 Multiprocessing CPU Core. available at http:\/\/www.gaisler.com\/doc\/leon3_product_sheet.pdf."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/648254.752562"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278606"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/647932.757246"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/646764.703964"},{"key":"e_1_3_2_1_7_1","first-page":"252","volume-title":"Differential Power Analysis in the Presence of Hardware Countermeasures. CHES 2000, LNCS 1965","author":"Clavier C.","year":"2000","unstructured":"C. Clavier , J.-S. Coron , and N. Dabbous . Differential Power Analysis in the Presence of Hardware Countermeasures. CHES 2000, LNCS 1965 : pp. 252 -- 263 , 2000 . C. Clavier, J.-S. Coron, and N. Dabbous. Differential Power Analysis in the Presence of Hardware Countermeasures. CHES 2000, LNCS 1965: pp. 252--263, 2000."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165780.1165783"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04138-9_1"},{"key":"e_1_3_2_1_10_1","first-page":"388","volume-title":"Differential Power Analysis. CRYPTO 1999","author":"Kocher P. C.","year":"1999","unstructured":"P. C. Kocher , J. Jaffe , and B. Jun . Differential Power Analysis. CRYPTO 1999 , LNCS 1666:pp. 388 -- 397 , 1999 . P. C. Kocher, J. Jaffe, and B. Jun. Differential Power Analysis. CRYPTO 1999, LNCS 1666:pp. 388--397, 1999."},{"key":"e_1_3_2_1_11_1","first-page":"187","article-title":"A Fast and Cache-timing Resistant Implementation of The AES. CT-RSA 2008","volume":"4964","author":"K\u00f6nighofer R.","year":"2008","unstructured":"R. K\u00f6nighofer . A Fast and Cache-timing Resistant Implementation of The AES. CT-RSA 2008 , LNCS 4964 :pp. 187 -- 202 , 2008 . R. K\u00f6nighofer. A Fast and Cache-timing Resistant Implementation of The AES. CT-RSA 2008, LNCS 4964:pp. 187--202, 2008.","journal-title":"LNCS"},{"key":"e_1_3_2_1_12_1","volume-title":"Power Analysis Attacks: Revealing the Secrets of Smart Cards","author":"Mangard S.","year":"2007","unstructured":"S. Mangard , E. Oswald , and T. Popp . Power Analysis Attacks: Revealing the Secrets of Smart Cards . Springer , 2007 . S. Mangard, E. Oswald, and T. Popp. Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer, 2007."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_9"},{"key":"e_1_3_2_1_14_1","unstructured":"NI\n      ST.\n     Annoucing the ADVANCED ENCRYPTION STANDARD (AES).\n   available at http:\/\/csrc.nist.gov\/publications\/fips\/fips197\/fips-197.pdf 2001\n  .  NIST. Annoucing the ADVANCED ENCRYPTION STANDARD (AES). available at http:\/\/csrc.nist.gov\/publications\/fips\/fips197\/fips-197.pdf 2001."},{"key":"e_1_3_2_1_15_1","first-page":"1","volume":"1007","author":"Nurmi J.","year":"2007","unstructured":"J. Nurmi . Processor Design. 10. 1007\/978 - 1 - 4020 -5530-0. Springer Netherlands, 2007 . J. Nurmi. Processor Design. 10.1007\/978-1-4020-5530-0. Springer Netherlands, 2007.","journal-title":"Processor Design. 10."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/11604938_23"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_13"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_26"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45238-6_11"},{"key":"e_1_3_2_1_20_1","first-page":"246","article-title":"A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation","volume":"2004","author":"Tiri K.","year":"2004","unstructured":"K. Tiri and I. Verbauwhede . A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation . Proceeding of DATE 2004 , vol. 1:pp. 246 -- 251 , 2004 . K. Tiri and I. Verbauwhede. A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. Proceeding of DATE 2004, vol. 1:pp. 246--251, 2004.","journal-title":"Proceeding of DATE"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.241"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289831"}],"event":{"name":"ESWeek '10: Sixth Embedded Systems Week","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","CEDA","IEEE CAS","IEEE CS"],"location":"Scottsdale Arizona USA","acronym":"ESWeek '10"},"container-title":["Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1878921.1878933","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1878921.1878933","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:09:04Z","timestamp":1750248544000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1878921.1878933"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10,24]]},"references-count":22,"alternative-id":["10.1145\/1878921.1878933","10.1145\/1878921"],"URL":"https:\/\/doi.org\/10.1145\/1878921.1878933","relation":{},"subject":[],"published":{"date-parts":[[2010,10,24]]},"assertion":[{"value":"2010-10-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}