{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T10:38:02Z","timestamp":1761561482778,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":43,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,10,24]],"date-time":"2010-10-24T00:00:00Z","timestamp":1287878400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,10,24]]},"DOI":"10.1145\/1878921.1878956","type":"proceedings-article","created":{"date-parts":[[2010,11,9]],"date-time":"2010-11-09T15:01:31Z","timestamp":1289314891000},"page":"237-246","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":25,"title":["E &lt; MC2"],"prefix":"10.1145","author":[{"given":"Arup","family":"Chakraborty","sequence":"first","affiliation":[{"name":"University of California, Irvine, Irvine, CA, USA"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA, USA"}]},{"given":"Amin","family":"Khajeh","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA, USA"}]},{"given":"Nikil","family":"Dutt","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA, USA"}]},{"given":"Ahmed","family":"Eltawil","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA, USA"}]},{"given":"Fadi","family":"Kurdahi","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2010,10,24]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"International Technology Roadmap for Semiconductors 2008. www.itrs.net  International Technology Roadmap for Semiconductors 2008. www.itrs.net"},{"volume-title":"ICCD","year":"2007","author":"Wong W.","key":"e_1_3_2_1_2_1"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1067915.1067921"},{"key":"e_1_3_2_1_4_1","unstructured":"F. Behmann \"Embedded.com - The ITRS process roadmap and nextgen embedded multicore SoC design \" Mar. 2009.  F. Behmann \"Embedded.com - The ITRS process roadmap and nextgen embedded multicore SoC design \" Mar. 2009."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.22"},{"key":"e_1_3_2_1_7_1","unstructured":"J. Fritts and W. Wolf \"Multi-level cache hierarchy evaluation for programmable media processors \" in Proc. IEEE SiPS 2000.  J. Fritts and W. Wolf \"Multi-level cache hierarchy evaluation for programmable media processors \" in Proc. IEEE SiPS 2000."},{"volume-title":"SPIE","year":"1999","author":"Fritts J.","key":"e_1_3_2_1_8_1"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0395"},{"key":"e_1_3_2_1_11_1","unstructured":"ARM Inc. \"ARM Cortex-A8 Technical Reference Manual.\" http:\/\/www.arm.com\/products\/CPUs\/ARM_Cortex-A8.html  ARM Inc. \"ARM Cortex-A8 Technical Reference Manual.\" http:\/\/www.arm.com\/products\/CPUs\/ARM_Cortex-A8.html"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.21141"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840407"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.53"},{"volume-title":"ICCD","year":"2007","author":"Makhzan M.","key":"e_1_3_2_1_15_1"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629395.1629431"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/832299.836546"},{"volume-title":"IEEE DSN","year":"2003","author":"Zhang Wei","key":"e_1_3_2_1_18_1"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.58"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696325"},{"volume-title":"DATE","year":"2009","author":"Khajeh A.","key":"e_1_3_2_1_22_1"},{"key":"e_1_3_2_1_23_1","unstructured":"L. Chang D. Fried etal \"Stable SRAM cell design for the 32 nm node and beyond \" in Proc. VLSI Tech 2005.  L. Chang D. Fried et al. \"Stable SRAM cell design for the 32 nm node and beyond \" in Proc. VLSI Tech 2005."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"crossref","unstructured":"J. Kulkarni K. Kim and K. Roy \"A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM \" IEEE JSSC vol. 42 2007.  J. Kulkarni K. Kim and K. Roy \"A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM \" IEEE JSSC vol. 42 2007.","DOI":"10.1145\/1283780.1283818"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696325"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"crossref","unstructured":"S. Schuster \"Multiple word\/bit line redundancy for semiconductor memories \" IEEE JSSC vol. 13 1978.  S. Schuster \"Multiple word\/bit line redundancy for semiconductor memories \" IEEE JSSC vol. 13 1978.","DOI":"10.1109\/JSSC.1978.1051122"},{"volume-title":"DATE","year":"2009","author":"Sasan A.","key":"e_1_3_2_1_27_1"},{"key":"e_1_3_2_1_28_1","unstructured":"P. Genua \"A Cache Primer \" Application Note Freescale Semiconductors 2004.  P. Genua \"A Cache Primer \" Application Note Freescale Semiconductors 2004."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/1331699.1331719"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2008.4681832"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.260635"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1229175.1229176"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383086"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1254766.1254773"},{"volume-title":"Prentice Hall","year":"1983","author":"Lin S.","key":"e_1_3_2_1_37_1"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"crossref","unstructured":"M. Khellah D. Somasekhar etal \"A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor \" IEEE JSSC vol. 42 2007.  M. Khellah D. Somasekhar et al. \"A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor \" IEEE JSSC vol. 42 2007.","DOI":"10.1109\/JSSC.2006.888357"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393953"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2005.115"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669126"},{"key":"e_1_3_2_1_43_1","unstructured":"Predictive Technology Model (PTM) http:\/\/ptm.asu.edu  Predictive Technology Model (PTM) http:\/\/ptm.asu.edu"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450125"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751937"}],"event":{"name":"ESWeek '10: Sixth Embedded Systems Week","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","CEDA","IEEE CAS","IEEE CS"],"location":"Scottsdale Arizona USA","acronym":"ESWeek '10"},"container-title":["Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1878921.1878956","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1878921.1878956","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:09:04Z","timestamp":1750248544000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1878921.1878956"}},"subtitle":["less energy through multi-copy cache"],"short-title":[],"issued":{"date-parts":[[2010,10,24]]},"references-count":43,"alternative-id":["10.1145\/1878921.1878956","10.1145\/1878921"],"URL":"https:\/\/doi.org\/10.1145\/1878921.1878956","relation":{},"subject":[],"published":{"date-parts":[[2010,10,24]]},"assertion":[{"value":"2010-10-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}