{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:31:22Z","timestamp":1750307482732,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":39,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,10,24]],"date-time":"2010-10-24T00:00:00Z","timestamp":1287878400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,10,24]]},"DOI":"10.1145\/1878961.1878977","type":"proceedings-article","created":{"date-parts":[[2010,11,9]],"date-time":"2010-11-09T15:01:31Z","timestamp":1289314891000},"page":"65-74","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Exploring programming model-driven QoS support for NoC-based platforms"],"prefix":"10.1145","author":[{"given":"Jaume","family":"Joven","sequence":"first","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}]},{"given":"Andrea","family":"Marongiu","sequence":"additional","affiliation":[{"name":"University of Bologna, Bologna, Italy"}]},{"given":"Federico","family":"Angiolini","sequence":"additional","affiliation":[{"name":"iNoCs SaRL, Lausanne, Switzerland"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"University of Bologna, Bologna, Italy"}]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[{"name":"EPFL, Lausanne, Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2010,10,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2004.1423874"},{"key":"e_1_3_2_1_2_1","unstructured":"AMBA 3 AXI overview 2005. http:\/\/www.arm.com\/products\/system-ip\/interconnect\/axi\/index.php.  AMBA 3 AXI overview 2005. http:\/\/www.arm.com\/products\/system-ip\/interconnect\/axi\/index.php."},{"key":"e_1_3_2_1_3_1","unstructured":"ARM AMBA 2.0 AHB-APB Overview 2005. http:\/\/www.arm.com\/products\/system-ip\/interconnect\/amba-design-kit.php.  ARM AMBA 2.0 AHB-APB Overview 2005. http:\/\/www.arm.com\/products\/system-ip\/interconnect\/amba-design-kit.php."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-005-6648-1"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_1_6_1","volume-title":"Networks on chips: Technology and Tools","author":"Benini L.","year":"2006","unstructured":"L. Benini and G. D. Micheli . Networks on chips: Technology and Tools . Morgan Kaufmann Publishers , San Francisco, CA, USA , 2006 . L. Benini and G. D. Micheli. Networks on chips: Technology and Tools. Morgan Kaufmann Publishers, San Francisco, CA, USA, 2006."},{"issue":"2","key":"e_1_3_2_1_7_1","first-page":"18","article-title":"Xpipes","volume":"4","author":"Bertozzi D.","year":"2004","unstructured":"D. Bertozzi and L. Benini . Xpipes : A Network-on-Chip Architecture for Gigascale Systems-on-Chip. 4 ( 2 ): 18 -- 31 , 2004 . D. Bertozzi and L. Benini. Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip. 4(2):18--31, 2004.","journal-title":"A Network-on-Chip Architecture for Gigascale Systems-on-Chip."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.36"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2003.07.004"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2009.6041343"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2009.5161107"},{"key":"e_1_3_2_1_12_1","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally W.","year":"2004","unstructured":"W. Dally and B. Towles . Principles and Practices of Interconnection Networks . Morgan Kaufmann Publishers Inc ., 2004 . W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2004."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.127260"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.7"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/EMPDP.2005.41"},{"key":"e_1_3_2_1_17_1","volume-title":"Interconnection Networks: An Engineering Approach","author":"Duato J.","year":"2003","unstructured":"J. Duato , S. Yalamanchili , and L. Ni . Interconnection Networks: An Engineering Approach . Morgan Kaufmann Publishers , 2003 . J. Duato, S. Yalamanchili, and L. Ni. Interconnection Networks: An Engineering Approach. Morgan Kaufmann Publishers, 2003."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/882452.874544"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.45"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874679"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0093"},{"key":"e_1_3_2_1_22_1","first-page":"2006","article-title":"A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach","author":"Panades I. Miro","year":"2006","unstructured":"I. Miro Panades , A. Greiner ., A. Sheibanyrad . A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach . In Nano-Net 2006 , 2006 . I. Miro Panades, A. Greiner., A. Sheibanyrad. A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. In Nano-Net 2006, 2006.","journal-title":"Nano-Net"},{"key":"e_1_3_2_1_23_1","volume-title":"Multiprocessor Systems-on-Chips. Morgan Kaufmann","author":"Jerraya A.","year":"2005","unstructured":"A. Jerraya and W. Wolf . Multiprocessor Systems-on-Chips. Morgan Kaufmann , Elsevier , 2005 . A. Jerraya and W. Wolf. Multiprocessor Systems-on-Chips. Morgan Kaufmann, Elsevier, 2005."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146981"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357790"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1007Is 10766-007-0042-5"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278510"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874819"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/962758.963394"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006717"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/1131481.1131519"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233573"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-008-0073-6"},{"key":"e_1_3_2_1_34_1","volume-title":"Open Core Protocol Standard","author":"International OCP","year":"2003","unstructured":"OCP International Partnership (OCP-IP). Open Core Protocol Standard , 2003 . http:\/\/www.ocpip.org\/home. OCP International Partnership (OCP-IP). Open Core Protocol Standard, 2003. http:\/\/www.ocpip.org\/home."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084856"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.79"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/789083.1022751"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379045"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.1"}],"event":{"name":"ESWeek '10: Sixth Embedded Systems Week","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","CEDA","IEEE CAS","IEEE CS"],"location":"Scottsdale Arizona USA","acronym":"ESWeek '10"},"container-title":["Proceedings of the eighth IEEE\/ACM\/IFIP international conference on Hardware\/software codesign and system synthesis"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1878961.1878977","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1878961.1878977","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:09:04Z","timestamp":1750248544000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1878961.1878977"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10,24]]},"references-count":39,"alternative-id":["10.1145\/1878961.1878977","10.1145\/1878961"],"URL":"https:\/\/doi.org\/10.1145\/1878961.1878977","relation":{},"subject":[],"published":{"date-parts":[[2010,10,24]]},"assertion":[{"value":"2010-10-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}