{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:31:22Z","timestamp":1750307482695,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,10,24]],"date-time":"2010-10-24T00:00:00Z","timestamp":1287878400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,10,24]]},"DOI":"10.1145\/1878961.1879011","type":"proceedings-article","created":{"date-parts":[[2010,11,9]],"date-time":"2010-11-09T15:01:31Z","timestamp":1289314891000},"page":"287-296","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["A performance model and code overlay generator for scratchpad enhanced embedded processors"],"prefix":"10.1145","author":[{"given":"Michael A.","family":"Baker","sequence":"first","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}]},{"given":"Amrit","family":"Panda","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}]},{"given":"Nikhil","family":"Ghadge","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}]},{"given":"Aniruddha","family":"Kadne","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}]},{"given":"Karam S.","family":"Chatha","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}]}],"member":"320","published-online":{"date-parts":[[2010,10,24]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Cell Broadband Engine Architecture. IBM Systems and Technology Group 2007.  Cell Broadband Engine Architecture. IBM Systems and Technology Group 2007."},{"key":"e_1_3_2_1_2_1","unstructured":"Software Development Kit for Multicore Acceleration Version 3.1 Programmer's Guide. IBM Systems and Technology Group 2008.  Software Development Kit for Multicore Acceleration Version 3.1 Programmer's Guide. IBM Systems and Technology Group 2008."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1023833.1023869"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.306.0603"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176887.1176933"},{"key":"e_1_3_2_1_6_1","unstructured":"gnu.org. GCC online documentation. http:\/\/gcc.gnu.org\/onlinedocs\/.  gnu.org. GCC online documentation. http:\/\/gcc.gnu.org\/onlinedocs\/."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118443"},{"volume-title":"Lecture Notes in Computer Science","year":"2008","author":"Pabalkar A.","key":"e_1_3_2_1_8_1"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859896"},{"key":"e_1_3_2_1_10_1","unstructured":"Power Architecture editors. An introduction to compiling for the Cell Broadband Engine architecture. IBM developerWorks 2006.  Power Architecture editors. An introduction to compiling for the Cell Broadband Engine architecture. IBM developerWorks 2006."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/361405.361407"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/581199.581247"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1151074.1151085"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878469"}],"event":{"name":"ESWeek '10: Sixth Embedded Systems Week","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","CEDA","IEEE CAS","IEEE CS"],"location":"Scottsdale Arizona USA","acronym":"ESWeek '10"},"container-title":["Proceedings of the eighth IEEE\/ACM\/IFIP international conference on Hardware\/software codesign and system synthesis"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1878961.1879011","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1878961.1879011","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:09:04Z","timestamp":1750248544000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1878961.1879011"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10,24]]},"references-count":14,"alternative-id":["10.1145\/1878961.1879011","10.1145\/1878961"],"URL":"https:\/\/doi.org\/10.1145\/1878961.1879011","relation":{},"subject":[],"published":{"date-parts":[[2010,10,24]]},"assertion":[{"value":"2010-10-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}