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Embed. Comput. Syst."],"published-print":{"date-parts":[[2010,12]]},"abstract":"<jats:p>Embedded systems with real-time constraints depend on a priori knowledge of worst-case execution times (WCETs) to determine if tasks meet deadlines. Static timing analysis derives bounds on WCETs but requires statically known loop bounds.<\/jats:p>\n          <jats:p>This work removes the constraint on known loop bounds through parametric analysis expressing WCETs as functions. Tighter WCETs are dynamically discovered to exploit slack by dynamic voltage scaling (DVS) saving 60% to 82% energy over DVS-oblivious techniques and showing savings close to more costly dynamic-priority DVS algorithms.<\/jats:p>\n          <jats:p>Overall, parametric analysis expands the class of real-time applications to programs with loop-invariant dynamic loop bounds while retaining tight WCET bounds.<\/jats:p>","DOI":"10.1145\/1880050.1880061","type":"journal-article","created":{"date-parts":[[2011,1,5]],"date-time":"2011-01-05T16:59:17Z","timestamp":1294246757000},"page":"1-34","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Parametric timing analysis and its application to dynamic voltage scaling"],"prefix":"10.1145","volume":"10","author":[{"given":"Sibin","family":"Mohan","sequence":"first","affiliation":[{"name":"North Carolina State University, Raleigh, NC"}]},{"given":"Frank","family":"Mueller","sequence":"additional","affiliation":[{"name":"North Carolina State University, Raleigh, NC"}]},{"given":"Michael","family":"Root","sequence":"additional","affiliation":[{"name":"Furman University, Greenville, SC"}]},{"given":"William","family":"Hawkins","sequence":"additional","affiliation":[{"name":"Furman University, Greenville, SC"}]},{"given":"Christopher","family":"Healy","sequence":"additional","affiliation":[{"name":"Furman University, Greenville, SC"}]},{"given":"David","family":"Whalley","sequence":"additional","affiliation":[{"name":"Florida State University, Tallahassee, FL"}]},{"given":"Emilio","family":"Vivancos","sequence":"additional","affiliation":[{"name":"Universidad Politecnica de Valencia, Valencia, Spain"}]}],"member":"320","published-online":{"date-parts":[[2011,1,7]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/780732.780771"},{"volume-title":"Proceedings of the Workshop on Compilers and Operating Systems for Low-Power. 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Aboughazaleh, N., Mosse, D., Childers, B., Melhem, R., and Craven, M. 2003. Collaborative operating system and compiler power management for real-time applications. In Proceedings of the Real-Time Embedded Technology and Applications Symposium. IEEE, Los Alamitos, CA."},{"key":"e_1_2_1_4_1","unstructured":"Aho A. V. Sethi R. and Ullman J. D. 1986. Compilers -- Principles Techniques and Tools. Addison-Wesley Upper Saddle River NJ.   Aho A. V. Sethi R. and Ullman J. D. 1986. Compilers -- Principles Techniques and Tools. Addison-Wesley Upper Saddle River NJ."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859659"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.2004.19"},{"volume-title":"Proceedings of the Real-Time Systems Symposium. IEEE","author":"Arnold R.","key":"e_1_2_1_8_1","unstructured":"Arnold , R. , Mueller , F. , Whalley , D. B. , and Harmon , M . 1994. Bounding worst-case instruction cache performance . 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