{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T12:21:39Z","timestamp":1767183699101,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2010,12,4]],"date-time":"2010-12-04T00:00:00Z","timestamp":1291420800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,12,4]]},"DOI":"10.1145\/1921249.1921259","type":"proceedings-article","created":{"date-parts":[[2010,12,22]],"date-time":"2010-12-22T14:41:30Z","timestamp":1293028890000},"page":"37-42","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology"],"prefix":"10.1145","author":[{"given":"Daniele","family":"Ludovici","sequence":"first","affiliation":[{"name":"TU Delft, Delft, The Netherlands"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgi N.","family":"Gaydadjiev","sequence":"additional","affiliation":[{"name":"TU Delft, Delft, The Netherlands"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco","family":"Gilabert","sequence":"additional","affiliation":[{"name":"University of Valencia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maria E.","family":"Gomez","sequence":"additional","affiliation":[{"name":"University of Valencia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Bertozzi","sequence":"additional","affiliation":[{"name":"University of Ferrara, Ferrara, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2010,12,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_1_2_1","volume-title":"Proc. of IEEE MuCoCos","author":"Gilabert F.","year":"2009","unstructured":"F. Gilabert , D. Ludovici , S. Medardoni , D. Bertozzi , L. Benini , G. N. Gaydadjiev , \" Designing Regular Network-on- Chip Topologies under Technology, Architecture and Software Constraints\". Proc. of IEEE MuCoCos , Fukuoka, Japan , 2009 . F. Gilabert, D. Ludovici, S. Medardoni, D. Bertozzi, L. Benini, G. N. Gaydadjiev, \"Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints\". Proc. of IEEE MuCoCos, Fukuoka, Japan, 2009."},{"key":"e_1_3_2_1_3_1","first-page":"107","volume-title":"Proc. of International Symposium on Network-on-Chip","author":"Gilabert F.","year":"2008","unstructured":"F. Gilabert , S. Medardoni , D. Bertozzi , L. Benini , M. E. G\u00f3mez , P. L\u00f3pez , J. Duato , \" Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework\". Proc. of International Symposium on Network-on-Chip , pp. 107 -- 116 , 2008 . F. Gilabert, S. Medardoni, D. Bertozzi, L. Benini, M. E. G\u00f3mez, P. L\u00f3pez, J. Duato, \"Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework\". Proc. of International Symposium on Network-on-Chip, pp. 107--116, 2008."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.79"},{"key":"e_1_3_2_1_5_1","first-page":"562","volume-title":"Proc. of DATE","author":"Ludovici D.","year":"2009","unstructured":"D. Ludovici , F. Gilabert , S. Medardoni , C. G\u00f3mez Requena , M. E. G\u00f3mez , P. L\u00f3pez , G. N. Gaydadjiev , D. Bertozzi , \" Assessing Fat-tree Topologies for Regular Network-on- Chip Design un der Nanoscale Technology Constraints\". Proc. of DATE , pp. 562 -- 565 , 2009 . D. Ludovici, F. Gilabert, S. Medardoni, C. G\u00f3mez Requena, M. E. G\u00f3mez, P. L\u00f3pez, G. N. Gaydadjiev, D. Bertozzi, \"Assessing Fat-tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints\". Proc. of DATE, pp. 562--565, 2009."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"e_1_3_2_1_7_1","unstructured":"Circuits Multi-Projects Multi-Project Circuits; http:\/\/cmp.imag.fr  Circuits Multi-Projects Multi-Project Circuits; http:\/\/cmp.imag.fr"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.1"},{"key":"e_1_3_2_1_9_1","unstructured":"TILE64 Processor Family online at http:\/\/www.tilera.com\/pdf\/ProBrief_Tile64_Web.pdf  TILE64 Processor Family online at http:\/\/www.tilera.com\/pdf\/ProBrief_Tile64_Web.pdf"},{"key":"e_1_3_2_1_10_1","first-page":"98","volume-title":"Proc. of ISSCC 2007","author":"S. Vangal","year":"2007","unstructured":"S. Vangal et al., \" An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS\". Proc. of ISSCC 2007 , pp. 98 -- 589 , 2007 . S. Vangal et al., \"An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS\". Proc. of ISSCC 2007, pp. 98--589, 2007."},{"key":"e_1_3_2_1_11_1","first-page":"302","volume-title":"Proc. of IEEE International Conference on Application-Speci↓c Systems, Architectures and Processors","author":"Bourduas S.","year":"2007","unstructured":"S. Bourduas , Z. Zilie , \" Latency Reduction of Global Tra ¡c in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing\". Proc. of IEEE International Conference on Application-Speci↓c Systems, Architectures and Processors , pp. 302 -- 307 , 2007 . S. Bourduas, Z. Zilie, \"Latency Reduction of Global Tra¡c in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing\". Proc. of IEEE International Conference on Application-Speci↓c Systems, Architectures and Processors, pp. 302--307, 2007."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/EIT.2007.4374481"},{"volume-title":"ACACES 2007, poster session with proceedings at the Summer School.","author":"Gilabert F.","key":"e_1_3_2_1_13_1","unstructured":"F. Gilabert , M. E. Gomez , P. J. Lopez , \" Performance Analysis of Multidimensional Topologies for NoC\". ACACES 2007, poster session with proceedings at the Summer School. F. Gilabert, M. E. Gomez, P. J. Lopez, \"Performance Analysis of Multidimensional Topologies for NoC\". ACACES 2007, poster session with proceedings at the Summer School."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1302494.1302781"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/1302494.1302857"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.40"},{"key":"e_1_3_2_1_17_1","first-page":"5866","volume-title":"Proc. of IEEE International Symposium on Circuits and Systems","volume":"6","author":"Kreutz M.","year":"2005","unstructured":"M. Kreutz , C. Marcon , L. Carro , N. Calazans , A. Susin , \" Energy and Latency Evaluation of NoC Topologies\". Proc. of IEEE International Symposium on Circuits and Systems , pp. 5866 -- 5869 Vol. 6 , 2005 . M. Kreutz, C. Marcon, L. Carro, N. Calazans, A. Susin, \"Energy and Latency Evaluation of NoC Topologies\". Proc. of IEEE International Symposium on Circuits and Systems, pp. 5866--5869 Vol. 6, 2005."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1231956.1231969"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996809"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.900725"},{"key":"e_1_3_2_1_21_1","first-page":"16","volume-title":"Proc. of International Symposium on System-on-Chip","author":"Coppola M.","year":"2004","unstructured":"M. Coppola , R. Locatelli , G. Maruccia , L. Pieralisi , A. Scandurra , \"Spidergon : a novel on-chip communication network \". Proc. of International Symposium on System-on-Chip , pp. 16 -- 18 , 2004 . M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra, \"Spidergon: a novel on-chip communication network\". Proc. of International Symposium on System-on-Chip, pp. 16--18, 2004."},{"key":"e_1_3_2_1_22_1","first-page":"884","volume-title":"Proceedings of DATE","author":"A. Jalabert","year":"2004","unstructured":"A. Jalabert et al., \"xpipesCompiler : a Tool for Instantiating Application Speci↓c Networks on Chip \". Proceedings of DATE , pp. 884 -- 889 , 2004 . A. Jalabert et al., \"xpipesCompiler: a Tool for Instantiating Application Speci↓c Networks on Chip\". Proceedings of DATE, pp. 884--889, 2004."}],"event":{"name":"NoCArc'10: Third International Workshop on Network on Chip Architectures","acronym":"NoCArc'10","location":"Atlanta Georgia USA"},"container-title":["Proceedings of the Third International Workshop on Network on Chip Architectures"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1921249.1921259","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1921249.1921259","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T12:08:41Z","timestamp":1750248521000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1921249.1921259"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12,4]]},"references-count":22,"alternative-id":["10.1145\/1921249.1921259","10.1145\/1921249"],"URL":"https:\/\/doi.org\/10.1145\/1921249.1921259","relation":{},"subject":[],"published":{"date-parts":[[2010,12,4]]},"assertion":[{"value":"2010-12-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}