{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:36:59Z","timestamp":1761647819904,"version":"3.41.0"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2010,9,14]],"date-time":"2010-09-14T00:00:00Z","timestamp":1284422400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2010,9,14]]},"abstract":"<jats:p>The implementation of high-precision floating-point applications on reconfigurable hardware requires large multipliers. Full multipliers are the core of floating-point multipliers. Truncated multipliers, trading resources for a well-controlled accuracy degradation, are useful building blocks in situations where a full multiplier is not needed.<\/jats:p>\n          <jats:p>This work studies the automated generation of such multipliers using the embedded multipliers and adders present in the DSP blocks of current FPGAs. The optimization of such multipliers is expressed as a tiling problem, where a tile represents a hardware multiplier, and super-tiles represent combinations of several hardware multipliers and adders, making efficient use of the DSP internal resources. This tiling technique is shown to adapt to full or truncated multipliers. It addresses arbitrary precisions including single, double but also the quadruple precision introduced by the IEEE-754-2008 standard and currently unsupported by processor hardware. An open-source implementation is provided in the FloPoCo project.<\/jats:p>","DOI":"10.1145\/1926367.1926380","type":"journal-article","created":{"date-parts":[[2011,1,24]],"date-time":"2011-01-24T14:58:13Z","timestamp":1295881093000},"page":"73-79","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":44,"title":["Multipliers for floating-point double precision and beyond on FPGAs"],"prefix":"10.1145","volume":"38","author":[{"given":"Sebastian","family":"Banescu","sequence":"first","affiliation":[{"name":"Technical University of Cluj-Napoca, Romania"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Florent","family":"de Dinechin","sequence":"additional","affiliation":[{"name":"LIP, projet Ar\u00e9naire, ENS de Lyon, Lyon Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bogdan","family":"Pasca","sequence":"additional","affiliation":[{"name":"LIP, projet Ar\u00e9naire, ENS de Lyon, Lyon Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Radu","family":"Tudoran","sequence":"additional","affiliation":[{"name":"Technical University of Cluj-Napoca, Romania"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,1,14]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ISE 11.4 CORE Generator IP.  ISE 11.4 CORE Generator IP."},{"key":"e_1_2_1_2_1","unstructured":"MegaWizard Plug-In Manager.  MegaWizard Plug-In Manager."},{"key":"e_1_2_1_3_1","volume-title":"Field-Programmable Logic and Applications","author":"Beuchat J.-L.","year":"2002","unstructured":"J.-L. Beuchat and A. Tisserand . Small multiplier-based multiplication and division operators for Virtex-II devices . In Field-Programmable Logic and Applications , 2002 . J.-L. Beuchat and A. Tisserand. Small multiplier-based multiplication and division operators for Virtex-II devices. In Field-Programmable Logic and Applications, 2002."},{"key":"e_1_2_1_4_1","volume-title":"Application-specific Systems, Architectures and Processors","author":"de Dinechin F.","year":"2010","unstructured":"F. de Dinechin , M. Joldes , and B. Pasca . Automatic generation of polynomial-based hardware architectures for function evaluation . In Application-specific Systems, Architectures and Processors . IEEE , 2010 . F. de Dinechin, M. Joldes, and B. Pasca. Automatic generation of polynomial-based hardware architectures for function evaluation. In Application-specific Systems, Architectures and Processors. IEEE, 2010."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272296"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.nima.2005.11.140"},{"key":"e_1_2_1_7_1","volume-title":"Digital Arithmetic","author":"Ercegovac M. D.","year":"2004","unstructured":"M. D. Ercegovac and T. Lang . Digital Arithmetic . Morgan Kaufmann Publishers , 2004 . M. D. Ercegovac and T. Lang. Digital Arithmetic. Morgan Kaufmann Publishers, 2004."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060074"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303135"},{"key":"e_1_2_1_10_1","volume-title":"IEEE Standard for Floating-Point Arithmetic","author":"IEEE Computer Society","year":"2008","unstructured":"IEEE Computer Society . IEEE Standard for Floating-Point Arithmetic , IEEE Std 754- 2008 . 2008. IEEE Computer Society. IEEE Standard for Floating-Point Arithmetic, IEEE Std 754-2008. 2008."},{"key":"e_1_2_1_11_1","volume-title":"Floating point unit generation and evaluation for FPGAs. Field-Programmable Custom Computing Machines, page 185","author":"Liang J.","year":"2003","unstructured":"J. Liang , R. Tessier , and O. Mencer . Floating point unit generation and evaluation for FPGAs. Field-Programmable Custom Computing Machines, page 185 , 2003 . J. Liang, R. Tessier, and O. Mencer. Floating point unit generation and evaluation for FPGAs. Field-Programmable Custom Computing Machines, page 185, 2003."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/1823389"},{"key":"e_1_2_1_13_1","first-page":"1344","volume-title":"Variable-Correction Truncated Floating Point Multipliers. In Asilomar Conference on Signals, Circuits and Systems","author":"Schulte M. J.","year":"2000","unstructured":"M. J. Schulte , K. E. Wires , and J. E. Stine . Variable-Correction Truncated Floating Point Multipliers. In Asilomar Conference on Signals, Circuits and Systems , pages 1344 -- 1348 , 2000 . M. J. Schulte, K. E. Wires, and J. E. Stine. Variable-Correction Truncated Floating Point Multipliers. In Asilomar Conference on Signals, Circuits and Systems, pages 1344--1348, 2000."},{"key":"e_1_2_1_14_1","first-page":"137","volume-title":"Engineering of Reconfigurable Systems and Algorithms","author":"Scrofano R.","year":"2005","unstructured":"R. Scrofano , G. Govindu , and V. K. Prasanna . A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing . In Engineering of Reconfigurable Systems and Algorithms , pages 137 -- 148 . CSREA Press , 2005 . R. Scrofano, G. Govindu, and V. K. Prasanna. A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing. In Engineering of Reconfigurable Systems and Algorithms, pages 137--148. CSREA Press, 2005."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723123"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968305"},{"key":"e_1_2_1_17_1","doi-asserted-by":"crossref","first-page":"574","DOI":"10.1007\/3-540-44687-7_59","volume-title":"Field-Programmable Logic and Applications","author":"Wires K. E.","year":"2001","unstructured":"K. E. Wires , M. J. Schulte , and D. McCarley . FPGA Resource Reduction Through Truncated Multiplication . In Field-Programmable Logic and Applications , pages 574 -- 583 . Springer-Verlag , 2001 . K. E. Wires, M. J. Schulte, and D. McCarley. FPGA Resource Reduction Through Truncated Multiplication. In Field-Programmable Logic and Applications, pages 574--583. Springer-Verlag, 2001."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1926367.1926380","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1926367.1926380","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:59:51Z","timestamp":1750244391000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1926367.1926380"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9,14]]},"references-count":17,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2010,9,14]]}},"alternative-id":["10.1145\/1926367.1926380"],"URL":"https:\/\/doi.org\/10.1145\/1926367.1926380","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2010,9,14]]},"assertion":[{"value":"2011-01-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}