{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:27:42Z","timestamp":1750307262061,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,1,23]],"date-time":"2011-01-23T00:00:00Z","timestamp":1295740800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002924","name":"Federaci\u00f3n Espa\u00f1ola de Enfermedades Raras","doi-asserted-by":"publisher","award":["TIN2009-14475-C04"],"award-info":[{"award-number":["TIN2009-14475-C04"]}],"id":[{"id":"10.13039\/501100002924","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,1,23]]},"DOI":"10.1145\/1930037.1930044","type":"proceedings-article","created":{"date-parts":[[2011,1,24]],"date-time":"2011-01-24T14:58:22Z","timestamp":1295881102000},"page":"23-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A power-efficient network on-chip topology"],"prefix":"10.1145","author":[{"given":"J.","family":"Camacho","sequence":"first","affiliation":[{"name":"Technical University of Valencia"}]},{"given":"J.","family":"Flich","sequence":"additional","affiliation":[{"name":"Technical University of Valencia"}]},{"given":"J.","family":"Duato","sequence":"additional","affiliation":[{"name":"Technical University of Valencia"}]},{"given":"H.","family":"Eberle","sequence":"additional","affiliation":[{"name":"Oracle Labs, California"}]},{"given":"W.","family":"Olesinski","sequence":"additional","affiliation":[{"name":"Oracle Labs, California"}]}],"member":"320","published-online":{"date-parts":[[2011,1,23]]},"reference":[{"volume-title":"Workshop on Comp. Arch. Evaluation Using Commercial Workloads.","author":"Alameldeen A. R.","key":"e_1_3_2_1_1_1","unstructured":"A. R. Alameldeen in Workshop on Comp. Arch. Evaluation Using Commercial Workloads. A. R. Alameldeen et al., \"Evaluating Non-deterministic Multi-threaded Commercial Workloads,\" in Workshop on Comp. Arch. Evaluation Using Commercial Workloads."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.83652"},{"key":"e_1_3_2_1_4_1","volume-title":"Int. Symp. High-Performance Computer Architecture","author":"Grot B.","year":"2009","unstructured":"B. Grot in Int. Symp. High-Performance Computer Architecture , 2009 . B. Grot et al., \"Express Cube Topologies for On-Chip Interconnects,\" in Int. Symp. High-Performance Computer Architecture, 2009."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"volume-title":"1st. Int. Work, on Network on Chip Architectures","year":"2008","key":"e_1_3_2_1_6_1","unstructured":"Wen-Hsiang Hu , \" DMesh: a Diagonally-Linked Mesh Network-on-Chip Architecture \", in 1st. Int. Work, on Network on Chip Architectures , 2008 . Wen-Hsiang Hu et al., \"DMesh: a Diagonally-Linked Mesh Network-on-Chip Architecture\", in 1st. Int. Work, on Network on Chip Architectures, 2008."},{"key":"e_1_3_2_1_7_1","volume-title":"April","author":"Kahng A.","year":"2009","unstructured":"A. Kahng , \" ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration,\" in DATE conf ., April 2009 . A. Kahng et al, \"ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration,\" in DATE conf., April 2009."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.15"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859896"},{"key":"e_1_3_2_1_12_1","unstructured":"Single-chip Cloud Computer at http:\/\/techresearch.intel.com.  Single-chip Cloud Computer at http:\/\/techresearch.intel.com."},{"key":"e_1_3_2_1_13_1","unstructured":"Teraflops Research Chip at http:\/\/www.intel.com\/pressroom\/kits\/teraflops.  Teraflops Research Chip at http:\/\/www.intel.com\/pressroom\/kits\/teraflops."},{"key":"e_1_3_2_1_14_1","unstructured":"Tile-Gx Processors Family at http:\/\/www.tilera.com.  Tile-Gx Processors Family at http:\/\/www.tilera.com."},{"key":"e_1_3_2_1_15_1","first-page":"98","volume-title":"Solid-State Circuits Conf.","author":"Vangal S.","year":"2007","unstructured":"S. Vangal 28 TFLOPS Network-on-Chip in 65nm CMOS,\" in Int . Solid-State Circuits Conf. , pages 98 -- 99 , Feb. 2007 . S. Vangal et al., \"An 80-Tile 1.28 TFLOPS Network-on-Chip in 65nm CMOS,\" in Int. Solid-State Circuits Conf., pages 98--99, Feb. 2007."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1016\/0167-739X(88)90007-6"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612254"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.89"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2009.170"}],"event":{"name":"INA-OCMC '11: On-Chip, Multi-Chip","acronym":"INA-OCMC '11","location":"Heraklion Greece"},"container-title":["Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1930037.1930044","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1930037.1930044","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:38Z","timestamp":1750243958000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1930037.1930044"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1,23]]},"references-count":20,"alternative-id":["10.1145\/1930037.1930044","10.1145\/1930037"],"URL":"https:\/\/doi.org\/10.1145\/1930037.1930044","relation":{},"subject":[],"published":{"date-parts":[[2011,1,23]]},"assertion":[{"value":"2011-01-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}