{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,20]],"date-time":"2026-05-20T21:11:21Z","timestamp":1779311481541,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,2,12]],"date-time":"2011-02-12T00:00:00Z","timestamp":1297468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,2,12]]},"DOI":"10.1145\/1947940.1947985","type":"proceedings-article","created":{"date-parts":[[2011,3,4]],"date-time":"2011-03-04T08:14:52Z","timestamp":1299226492000},"page":"210-214","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Performance analysis of FPGA interconnect fabric for ultra-low power applications"],"prefix":"10.1145","author":[{"given":"S. D.","family":"Pable","sequence":"first","affiliation":[{"name":"Aligarh Muslim University, Aligarh, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohd.","family":"Hasan","sequence":"additional","affiliation":[{"name":"Aligarh Muslim University, Aligarh, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,2,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/283702"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.920822"},{"key":"e_1_3_2_1_3_1","unstructured":"Wayne Wolf FPGA-Based System Design Pearson education"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120984"},{"key":"e_1_3_2_1_5_1","volume-title":"IEEE","author":"George","year":"2009","unstructured":"George V. Leming and Kundan Nepal, Low-power FPGA routing switches using adaptive body biasing techniques, in IEEE 2009."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968285"},{"key":"e_1_3_2_1_7_1","first-page":"32","volume-title":"proc. of IEEE","author":"Jason","year":"2004","unstructured":"Jason H. Anderson and Farid N. Najm, A noval low power FPGA routing switch, CICC, in proc. of IEEE, pp. 32-3-1 to 32-3-4, November 2004."},{"key":"e_1_3_2_1_8_1","first-page":"178","volume-title":"Engineering and Technology","author":"A.","year":"2009","unstructured":"A. K. kureshi and Mohd. Hasan, Analysis of CNT bundle and its comparision with copper for FPGA interconnect, in International Journal of Applied Science, Engineering and Technology, March 2009, pp 178--183."},{"key":"e_1_3_2_1_9_1","volume-title":"Anantha P. Chandrakasan, Sub-threshold design for ultra low-power systems","author":"Alicewang","unstructured":"Alicewang, Benton calhoun, Anantha P. Chandrakasan, Sub-threshold design for ultra low-power systems, Springer publication."},{"key":"e_1_3_2_1_10_1","unstructured":"Xilinx Corporation Virtex-II 1.5V Field Programmable Gate Arrays DS0331-1 Version 2.5 April 2001"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852293"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/227375"},{"key":"e_1_3_2_1_13_1","unstructured":"http:\/\/www.eas.asu.edu\/ptm\/"},{"key":"e_1_3_2_1_14_1","first-page":"64","volume-title":"IET Circuit and device system 3(2)","author":"Vijaykrishnan S. N.","year":"2009","unstructured":"S. N. Vijaykrishnan, A. Neuwodt, Y. Masood, Predicting the performance and reliability of future FPGAs routing architectures with CNT interconnects, in IET Circuit and device system 3(2) pp. 64--75, 2009."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2017443"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035453"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.909030"},{"key":"e_1_3_2_1_18_1","volume-title":"Double gate-MOSFET subthreshold circuits for ultralow power applications","author":"Kimn Jae-Joon","unstructured":"Jae-Joon Kimn and Kaushik Roy, Double gate-MOSFET subthreshold circuits for ultralow power applications, IEEE transaction on Electron devices, vol. 51, no. 9, pp. 1468--1473, sep. 2004."},{"key":"e_1_3_2_1_19_1","first-page":"431","volume-title":"52nd IEEE International Midwest symposium on Circuits and Systems","author":"Sherif","year":"2009","unstructured":"Sherif A. Tawfik and Volkan Kursun, FinFET technology development guidelines for higher performance, low power and stronger resilience to parameter variation, 52nd IEEE International Midwest symposium on Circuits and Systems, pp. 431--434, Aug. 2009."}],"event":{"name":"ICCCS '11: International Conference on Communication, Computing & Security","location":"Rourkela Odisha India","acronym":"ICCCS '11"},"container-title":["Proceedings of the 2011 International Conference on Communication, Computing &amp; Security"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1947940.1947985","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1947940.1947985","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,20]],"date-time":"2026-05-20T20:31:06Z","timestamp":1779309066000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1947940.1947985"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2,12]]},"references-count":19,"alternative-id":["10.1145\/1947940.1947985","10.1145\/1947940"],"URL":"https:\/\/doi.org\/10.1145\/1947940.1947985","relation":{},"subject":[],"published":{"date-parts":[[2011,2,12]]},"assertion":[{"value":"2011-02-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}