{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T08:47:45Z","timestamp":1774687665937,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":32,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,3,27]],"date-time":"2011-03-27T00:00:00Z","timestamp":1301184000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,3,27]]},"DOI":"10.1145\/1960397.1960417","type":"proceedings-article","created":{"date-parts":[[2011,3,22]],"date-time":"2011-03-22T12:25:29Z","timestamp":1300796729000},"page":"81-88","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Assembling 2D blocks into 3D chips"],"prefix":"10.1145","author":[{"given":"Johann","family":"Knechtel","sequence":"first","affiliation":[{"name":"University of Michigan, Ann Arbor USA & Dresden University of Technology, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Igor L.","family":"Markov","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor, MI, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jens","family":"Lienig","sequence":"additional","affiliation":[{"name":"Dresden University of Technology, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,3,27]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/505388.505392"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1007\/978-1-4419-0784-4_4","volume-title":"Thermal-aware 3D floorplan. Three Dimensional Integrated Circuit Design","author":"Cong J.","year":"2010","unstructured":"J. Cong , Y. Ma . Thermal-aware 3D floorplan. Three Dimensional Integrated Circuit Design , pp. 63 -- 102 . Springer US , 2010 . J. Cong, Y. Ma. Thermal-aware 3D floorplan. Three Dimensional Integrated Circuit Design, pp. 63--102. Springer US, 2010."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"e_1_3_2_1_4_1","first-page":"220","volume-title":"ICCAD '07","author":"Ferri C.","unstructured":"C. Ferri , S. Reda , R. I. Bahar . Strategies for improving the parametric yield and profits of 3D ICs . ICCAD '07 , pp. 220 -- 226 . C. Ferri, S. Reda, R. I. Bahar. Strategies for improving the parametric yield and profits of 3D ICs. ICCAD '07, pp. 220--226."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1572471.1572485"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1016\/0020-0190(81)90111-3"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810285"},{"key":"e_1_3_2_1_8_1","volume-title":"Algorithmic graph theory and perfect graphs","author":"Golumbic M. C.","year":"2004","unstructured":"M. C. Golumbic . Algorithmic graph theory and perfect graphs . Elsevier , 2004 . M. C. Golumbic. Algorithmic graph theory and perfect graphs. Elsevier, 2004."},{"key":"e_1_3_2_1_9_1","volume-title":"CICC '10","author":"Healy M. B.","unstructured":"M. B. Healy Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory . CICC '10 . M. B. Healy et al. Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC '10."},{"key":"e_1_3_2_1_10_1","first-page":"166","volume-title":"DATE '10","author":"Hsieh A.-C.","unstructured":"A.-C. Hsieh TSV redundancy : Architecture and design issues in 3D IC . DATE '10 , pp. 166 -- 171 . A.-C. Hsieh et al. TSV redundancy: Architecture and design issues in 3D IC. DATE '10, pp. 166--171."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1016\/0196-6774(83)90012-3"},{"key":"e_1_3_2_1_13_1","unstructured":"International technology roadmap for semiconductors. http:\/\/www.itrs.net\/Links\/2009ITRS\/Home2009.htm.  International technology roadmap for semiconductors. http:\/\/www.itrs.net\/Links\/2009ITRS\/Home2009.htm."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687434"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687524"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1572471.1572486"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.125"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687519"},{"key":"e_1_3_2_1_19_1","first-page":"56","volume-title":"IITC '09","author":"Lee Y.-J.","unstructured":"Y.-J. Lee , M. Healy , S. K. Lim . Co-design of reliable signal and power interconnects in 3D stacked ICs . IITC '09 , pp. 56 -- 58 . Y.-J. Lee, M. Healy, S. K. Lim. Co-design of reliable signal and power interconnects in 3D stacked ICs. IITC '09, pp. 56--58."},{"key":"e_1_3_2_1_20_1","first-page":"209","volume-title":"ASP-DAC '08","author":"Li X.","unstructured":"X. Li LP based white space redistribution for thermal via planning and performance optimization in 3D ICs . ASP-DAC '08 , pp. 209 -- 212 . X. Li et al. LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC '08, pp. 209--212."},{"key":"e_1_3_2_1_21_1","first-page":"347","volume-title":"ASP-DAC '09","author":"Li X.","unstructured":"X. Li , Y. Ma , X. Hong . A novel thermal optimization flow using incremental floorplanning for 3D ICs . ASP-DAC '09 , pp. 347 -- 352 . X. Li, Y. Ma, X. Hong. A novel thermal optimization flow using incremental floorplanning for 3D ICs. ASP-DAC '09, pp. 347--352."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123048"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1142155.1142159"},{"key":"e_1_3_2_1_24_1","first-page":"598","volume-title":"ICCAD '08","author":"Loi I.","unstructured":"I. Loi A low-overhead fault tolerance scheme for TSV-based 3D network on chip links . ICCAD '08 , pp. 598 -- 602 . I. Loi et al. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. ICCAD '08, pp. 598--602."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391962.1391975"},{"key":"e_1_3_2_1_26_1","volume-title":"Combinatorial Optimization: Algorithms and Complexity","author":"Papadimitriou C. H.","year":"1998","unstructured":"C. H. Papadimitriou , K. Steiglitz . Combinatorial Optimization: Algorithms and Complexity . Dover Publications , 1998 . C. H. Papadimitriou, K. Steiglitz. Combinatorial Optimization: Algorithms and Complexity. Dover Publications, 1998."},{"key":"e_1_3_2_1_27_1","volume-title":"Timing","author":"Sapatnekar S. S.","year":"2004","unstructured":"S. S. Sapatnekar . Timing . Kluwer , 2004 . S. S. Sapatnekar. Timing. Kluwer, 2004."},{"key":"e_1_3_2_1_28_1","first-page":"763","volume-title":"A criticality-driven microarchitectural three dimensional (3D) floorplanner. ASP-DAC ';09","author":"Sridharan S.","unstructured":"S. Sridharan A criticality-driven microarchitectural three dimensional (3D) floorplanner. ASP-DAC ';09 , pp. 763 -- 768 . S. Sridharan et al. A criticality-driven microarchitectural three dimensional (3D) floorplanner. ASP-DAC ';09, pp. 763--768."},{"key":"e_1_3_2_1_29_1","first-page":"267","volume-title":"ICCD '07","author":"Wong E.","unstructured":"E. Wong , S. K. Lim . Whitespace redistribution for thermal via insertion in 3D stacked ICs . ICCD '07 , pp. 267 -- 272 . E. Wong, S. K. Lim. Whitespace redistribution for thermal via insertion in 3D stacked ICs. ICCD '07, pp. 267 --272."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837313"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837476"},{"key":"e_1_3_2_1_32_1","first-page":"590","volume-title":"ICCAD '07","author":"Zhou P.","unstructured":"P. Zhou : scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits . ICCAD '07 , pp. 590 -- 597 . P. Zhou et al. 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD '07, pp. 590--597."}],"event":{"name":"ISPD'11: International Symposium on Physical Design","location":"Santa Barbara CA USA","acronym":"ISPD'11","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2011 international symposium on Physical design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1960397.1960417","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1960397.1960417","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:48:53Z","timestamp":1750240133000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1960397.1960417"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3,27]]},"references-count":32,"alternative-id":["10.1145\/1960397.1960417","10.1145\/1960397"],"URL":"https:\/\/doi.org\/10.1145\/1960397.1960417","relation":{},"subject":[],"published":{"date-parts":[[2011,3,27]]},"assertion":[{"value":"2011-03-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}