{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:25:41Z","timestamp":1750307141249,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,3,27]],"date-time":"2011-03-27T00:00:00Z","timestamp":1301184000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,3,27]]},"DOI":"10.1145\/1960397.1960436","type":"proceedings-article","created":{"date-parts":[[2011,3,22]],"date-time":"2011-03-22T12:25:29Z","timestamp":1300796729000},"page":"167-174","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Lagrangian relaxation for gate implementation selection"],"prefix":"10.1145","author":[{"given":"Yi-Le","family":"Huang","sequence":"first","affiliation":[{"name":"Texas A&amp;M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiang","family":"Hu","sequence":"additional","affiliation":[{"name":"Texas A&amp;M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weiping","family":"Shi","sequence":"additional","affiliation":[{"name":"Texas A&amp;M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,3,27]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"326","article-title":"TILOS: A posynomial programming approach to transistor sizing","author":"Fishburn J.","year":"1985","unstructured":"J. Fishburn and A. Dunlop . \" TILOS: A posynomial programming approach to transistor sizing ,\" In Proc. of ICCAD , pp. 326 -- 328 , 1985 . J. Fishburn and A. Dunlop. \"TILOS: A posynomial programming approach to transistor sizing,\" In Proc. of ICCAD, pp. 326--328, 1985.","journal-title":"Proc. of ICCAD"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.748196"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313900"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.844304"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774628"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871545"},{"key":"e_1_3_2_1_7_1","first-page":"704","article-title":"Discrete Vt assignment and gate sizing using a self-snapping continuous formulation","author":"Shah S.","year":"2005","unstructured":"S. Shah , A. Srivastava , D. Sharma , D. Sylvester , D. Balaauw , and V. Zolotov . \" Discrete Vt assignment and gate sizing using a self-snapping continuous formulation ,\" In Proc. of ICCAD , pp. 704 -- 710 , 2005 . S. Shah, A. Srivastava, D. Sharma, D. Sylvester, D. Balaauw, and V. Zolotov. \"Discrete Vt assignment and gate sizing using a self-snapping continuous formulation,\" In Proc. of ICCAD, pp. 704--710, 2005.","journal-title":"Proc. of ICCAD"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309975"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120881"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393937"},{"key":"e_1_3_2_1_11_1","first-page":"111","article-title":"Gate sizing by Lagrangian relaxation revisited","author":"Wang J.","year":"2007","unstructured":"J. Wang , D. Das , and H. Zhou . \" Gate sizing by Lagrangian relaxation revisited ,\" In Proc. of ICCAD , pp. 111 -- 118 , 2007 . J. Wang, D. Das, and H. Zhou. \"Gate sizing by Lagrangian relaxation revisited,\" In Proc. of ICCAD, pp. 111--118, 2007.","journal-title":"Proc. of ICCAD"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.771182"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.851993"},{"key":"e_1_3_2_1_14_1","first-page":"196","article-title":"ConvexFit: An optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing","author":"Roy S.","year":"2005","unstructured":"S. Roy , W. Chen , and C.C. Chen . \" ConvexFit: An optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing ,\" In Proc. of ICCAD , pp. 196 -- 204 , 2005 . S. Roy, W. Chen, and C.C. Chen. \"ConvexFit: An optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing,\" In Proc. of ICCAD, pp. 196--204, 2005.","journal-title":"Proc. of ICCAD"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278690"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514940"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774631"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.1000"},{"key":"e_1_3_2_1_19_1","volume-title":"Static Timing Analysis for Nanometer Designs","author":"Chadha R.","year":"2009","unstructured":"R. Chadha and J. Bhasker . Static Timing Analysis for Nanometer Designs , Springer , 2009 . R. Chadha and J. Bhasker. Static Timing Analysis for Nanometer Designs, Springer, 2009."},{"key":"e_1_3_2_1_20_1","volume-title":"SIS: a system for sequential circuit synthesis,\" Electron. Res. Lab","author":"Sentovich E.M.","year":"1992","unstructured":"E.M. Sentovich , K.J. Singh , L. Lavagno , C. Moon , R. Murgai , A. Saldanha , H. Savoj , P.R. Stephan , R.K. Brayton , and A.L. Snagiovanni . \" SIS: a system for sequential circuit synthesis,\" Electron. Res. Lab ., Univ. California , Berkeley, CA , Mem. UCB\/ERL M92\/41, May 1992 . E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A.L. Snagiovanni. \"SIS: a system for sequential circuit synthesis,\" Electron. Res. Lab., Univ. California, Berkeley, CA, Mem. UCB\/ERL M92\/41, May 1992."},{"volume-title":"UCLA","key":"e_1_3_2_1_21_1","unstructured":"CPMO-constrained placement by multilevel optimization. http:\/\/ballade.cs.ucla.edu\/cpmo. Computer Science Department , UCLA CPMO-constrained placement by multilevel optimization. http:\/\/ballade.cs.ucla.edu\/cpmo. Computer Science Department, UCLA"}],"event":{"name":"ISPD'11: International Symposium on Physical Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Santa Barbara CA USA","acronym":"ISPD'11"},"container-title":["Proceedings of the 2011 international symposium on Physical design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1960397.1960436","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1960397.1960436","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:48:53Z","timestamp":1750240133000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1960397.1960436"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3,27]]},"references-count":21,"alternative-id":["10.1145\/1960397.1960436","10.1145\/1960397"],"URL":"https:\/\/doi.org\/10.1145\/1960397.1960436","relation":{},"subject":[],"published":{"date-parts":[[2011,3,27]]},"assertion":[{"value":"2011-03-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}