{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:27:48Z","timestamp":1750307268207,"version":"3.41.0"},"reference-count":39,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2011,6,1]],"date-time":"2011-06-01T00:00:00Z","timestamp":1306886400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2011,6]]},"abstract":"<jats:p>Power Management Units (PMUs) are large integrated circuits consisting of many predesigned mixed-signal components. PMU integration poses a serious verification problem considering the size of the integrated circuit and the complexity of analog simulation. In this article we present an approach for automatic generation of behavioral models for PMU components from top-down skeleton models, fitted with parameter values estimated by bottom-up parameter extraction algorithms. It is shown that replacing PMU components with these autogenerated hybrid automata-based abstract behavioral models enables significant simulation speedup (&gt; 20X on our industrial test cases) and helps in early detection of integration errors. The article also justifies the level of accuracy in our models with respect to the goal of verifying integrated PMUs. The approach presented in this work is implemented in the form of a tool suite called Chassis.<\/jats:p>","DOI":"10.1145\/1970353.1970367","type":"journal-article","created":{"date-parts":[[2011,6,14]],"date-time":"2011-06-14T14:44:54Z","timestamp":1308062694000},"page":"1-30","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Chassis"],"prefix":"10.1145","volume":"16","author":[{"given":"Antara","family":"Ain","sequence":"first","affiliation":[{"name":"IIT Kharagpur"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Debjit","family":"Pal","sequence":"additional","affiliation":[{"name":"IIT Kharagpur"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pallab","family":"Dasgupta","sequence":"additional","affiliation":[{"name":"IIT Kharagpur"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Siddhartha","family":"Mukhopadhyay","sequence":"additional","affiliation":[{"name":"IIT Kharagpur"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajdeep","family":"Mukhopadhyay","sequence":"additional","affiliation":[{"name":"National Semiconductor Corp."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John","family":"Gough","sequence":"additional","affiliation":[{"name":"National Semiconductor Corp."}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/0304-3975(94)00202-T"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of IEEE International Symposium on Circuits and Systems.","volume":"6","author":"Arsintescu B.","unstructured":"Arsintescu , B. , Charbon , E. , Malavasi , E. , and Kao , W . 1998. AC constraint transformation for top-down analog design . In Proceedings of IEEE International Symposium on Circuits and Systems. Vol. 6 . 126--130. Arsintescu, B., Charbon, E., Malavasi, E., and Kao, W. 1998. AC constraint transformation for top-down analog design. In Proceedings of IEEE International Symposium on Circuits and Systems. Vol. 6. 126--130."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.728849"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems.","volume":"5","author":"Chandra N.","unstructured":"Chandra , N. and Roberts , G . 2001. Top-Down analog design methodology using Matlab and Simulink . In Proceedings of the IEEE International Symposium on Circuits and Systems. Vol. 5 . 319--322. Chandra, N. and Roberts, G. 2001. Top-Down analog design methodology using Matlab and Simulink. In Proceedings of the IEEE International Symposium on Circuits and Systems. Vol. 5. 319--322."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008330914786"},{"key":"e_1_2_1_6_1","doi-asserted-by":"crossref","unstructured":"Erickson R. and Maksimovic D. 2001. Fundamentals of Power Electronics. Kluwer Academic Publishers. Erickson R. and Maksimovic D. 2001. Fundamentals of Power Electronics . Kluwer Academic Publishers.","DOI":"10.1007\/b100747"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/WGEC.2009.92"},{"volume-title":"Proceeedings of the IEEE International Symposium on Circuits and Systems 6. 17--20","author":"Fernandez F. V.","key":"e_1_2_1_8_1","unstructured":"Fernandez , F. V. , Perez-Verdu , B. , and Rodriguez-Vazquez , A . 1998. Behavioral modeling of PWL analog circuits using symbolic analysis . In Proceeedings of the IEEE International Symposium on Circuits and Systems 6. 17--20 . Fernandez, F. V., Perez-Verdu, B., and Rodriguez-Vazquez, A. 1998. Behavioral modeling of PWL analog circuits using symbolic analysis. In Proceeedings of the IEEE International Symposium on Circuits and Systems 6. 17--20."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/YCICT.2009.5382336"},{"volume-title":"Proceedings of the International Conference on Solid-State and Integrated-Circuit Technology. 424--427","author":"Garcia-Moreno E.","key":"e_1_2_1_10_1","unstructured":"Garcia-Moreno , E. , Iniguez , B. , and Picos , R . 2008. Directed genetic algorithms for otft model parameter extraction . In Proceedings of the International Conference on Solid-State and Integrated-Circuit Technology. 424--427 . Garcia-Moreno, E., Iniguez, B., and Picos, R. 2008. Directed genetic algorithms for otft model parameter extraction. In Proceedings of the International Conference on Solid-State and Integrated-Circuit Technology. 424--427."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.814256"},{"key":"e_1_2_1_13_1","volume-title":"Proceedings of the IEEE International Conference on Neural Networks.","volume":"4","author":"Kennedy J.","year":"1942","unstructured":"Kennedy , J. and Eberhart , R . 1995. Particle swarm optimization . In Proceedings of the IEEE International Conference on Neural Networks. Vol. 4 . 1942 --1947. Kennedy, J. and Eberhart, R. 1995. Particle swarm optimization. In Proceedings of the IEEE International Conference on Neural Networks. Vol. 4. 1942--1947."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.ejor.2004.08.047"},{"key":"e_1_2_1_15_1","unstructured":"Kendurt K. 2003. Principles of top-down mixed-signal design. www.designers-guide.org\/Design\/tdd-principles.pdf. Kendurt K. 2003. Principles of top-down mixed-signal design. www.designers-guide.org\/Design\/tdd-principles.pdf."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.958340"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.958341"},{"volume-title":"Proceedings of the Parallel and Distributed Processing Symposium.","author":"Li Y.","key":"e_1_2_1_18_1","unstructured":"Li , Y. and Cho , Y . -Y. 2006. Parallel genetic algorithm for spice model parameter extraction . In Proceedings of the Parallel and Distributed Processing Symposium. Li, Y. and Cho, Y.-Y. 2006. Parallel genetic algorithm for spice model parameter extraction. In Proceedings of the Parallel and Distributed Processing Symposium."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2008.02.021"},{"key":"e_1_2_1_20_1","unstructured":"LM3670. 2006. A DC-DC converter from national semiconductor. http:\/\/www.national.com\/pf\/LM\/LM3670.html. LM3670 . 2006. A DC-DC converter from national semiconductor. http:\/\/www.national.com\/pf\/LM\/LM3670.html."},{"key":"e_1_2_1_21_1","unstructured":"Lourakis M. 2005. A brief description of the levenberg-marquardt algorithm implemented by levmar. www.ics.forth.gr\/~lourakis\/levmar\/levmar.pdf. Lourakis M. 2005. A brief description of the levenberg-marquardt algorithm implemented by levmar. www.ics.forth.gr\/~lourakis\/levmar\/levmar.pdf."},{"key":"e_1_2_1_22_1","unstructured":"LP3918. 2009. A pmu chip from national semiconductor. http:\/\/www.national.com\/pf\/LP\/LP3918.html. LP3918 . 2009. A pmu chip from national semiconductor. http:\/\/www.national.com\/pf\/LP\/LP3918.html."},{"key":"e_1_2_1_23_1","doi-asserted-by":"crossref","unstructured":"Maehne T. Vachoux A. Giroud F. and Contaldo M. 2009. A vhdl-ams modeling methodology for top-down\/bottom-up design of rf systems. Forum Specif. Des. Lang. 1--7. Maehne T. Vachoux A. Giroud F. and Contaldo M. 2009. A vhdl-ams modeling methodology for top-down\/bottom-up design of rf systems. Forum Specif. Des. Lang. 1--7.","DOI":"10.1007\/978-90-481-9304-2_10"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01239360"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the International Symposium on Circuits and Systems.","volume":"3","author":"Mantooth H.","unstructured":"Mantooth , H. , Ren , L. , Huang , X. , Feng , Y. , and Zheng , W . 2003. A survey of bottom-up behavioral modeling methods for analog circuits . In Proceedings of the International Symposium on Circuits and Systems. Vol. 3 . 910--913. Mantooth, H., Ren, L., Huang, X., Feng, Y., and Zheng, W. 2003. A survey of bottom-up behavioral modeling methods for analog circuits. In Proceedings of the International Symposium on Circuits and Systems. Vol. 3. 910--913."},{"volume-title":"Proceedings of the IEEE International Behavioral Modeling and Simulation Workshop. 128--133","author":"Mu S.","key":"e_1_2_1_26_1","unstructured":"Mu , S. and Laisne , M . 2005. Mixed-Signal modeling using simulink based-c . In Proceedings of the IEEE International Behavioral Modeling and Simulation Workshop. 128--133 . Mu, S. and Laisne, M. 2005. Mixed-Signal modeling using simulink based-c. In Proceedings of the IEEE International Behavioral Modeling and Simulation Workshop. 128--133."},{"volume-title":"Proceedings of the 12th VLSI Design and Test Symposium.","author":"Mukhopadhyay R.","key":"e_1_2_1_27_1","unstructured":"Mukhopadhyay , R. , Ain , A. , Panda , S. , Dasgupta , P. , Mukhopadhyay , S. , and Gough , J . 2008. Mode based functional partitioning of design intent for behavioral modeling of large AMS circuits . In Proceedings of the 12th VLSI Design and Test Symposium. Mukhopadhyay, R., Ain, A., Panda, S., Dasgupta, P., Mukhopadhyay, S., and Gough, J. 2008. Mode based functional partitioning of design intent for behavioral modeling of large AMS circuits. In Proceedings of the 12th VLSI Design and Test Symposium."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/968878.969039"},{"key":"e_1_2_1_29_1","first-page":"549","article-title":"Modeling and simulation of phase-locked loop with verilog-A description for top-down design","volume":"1","author":"Oura T.","year":"2004","unstructured":"Oura , T. , Hiraku , Y. , Suzuk , T. , and Asai , H. 2004 . Modeling and simulation of phase-locked loop with verilog-A description for top-down design . In Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems 1. 549 -- 552 . Oura, T., Hiraku, Y., Suzuk, T., and Asai, H. 2004. Modeling and simulation of phase-locked loop with verilog-A description for top-down design. In Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems 1. 549--552.","journal-title":"Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.62"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.806605"},{"volume-title":"Proceedings of IEEE International Workshop on Behavioral Modeling and Simulation. 71--74","author":"Root D.","key":"e_1_2_1_33_1","unstructured":"Root , D. , Wood , J. , Tufillaro , N. , Schreurs , D. , and Pekker , A . 2002. Systematic behavioral modeling of nonlinear microwave\/RF circuits in the time domain using techniques from nonlinear dynamical systems . In Proceedings of IEEE International Workshop on Behavioral Modeling and Simulation. 71--74 . Root, D., Wood, J., Tufillaro, N., Schreurs, D., and Pekker, A. 2002. Systematic behavioral modeling of nonlinear microwave\/RF circuits in the time domain using techniques from nonlinear dynamical systems. In Proceedings of IEEE International Workshop on Behavioral Modeling and Simulation. 71--74."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008202821328"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0020-0190(02)00447-7"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.801098"},{"volume-title":"Proceedings of Design, Automation and Test in Europe Conference. 716--720","author":"Vandenbussche J.","key":"e_1_2_1_37_1","unstructured":"Vandenbussche , J. , Donnay , S. , Leyn , F. , Gielen , G. , and Sansen , W . 1998. Hierarchical top-down design of analog sensor interfaces: From system-level specifications down to silicon . In Proceedings of Design, Automation and Test in Europe Conference. 716--720 . Vandenbussche, J., Donnay, S., Leyn, F., Gielen, G., and Sansen, W. 1998. Hierarchical top-down design of analog sensor interfaces: From system-level specifications down to silicon. In Proceedings of Design, Automation and Test in Europe Conference. 716--720."},{"key":"e_1_2_1_38_1","unstructured":"VerilogA LRM. 2009. http:\/\/www.eda.org\/verilog-ams\/htmlpages\/lit.html. VerilogA LRM . 2009. http:\/\/www.eda.org\/verilog-ams\/htmlpages\/lit.html."},{"volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS08)","author":"Xia L.","key":"e_1_2_1_39_1","unstructured":"Xia , L. , Bell , I. , and Wilkinson , A . 2008. A novel approach for automated model generation . In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS08) . 504--507. Xia, L., Bell, I., and Wilkinson, A. 2008. A novel approach for automated model generation. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS08). 504--507."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775956"},{"volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems. 5186--5189","author":"Zheng W.","key":"e_1_2_1_41_1","unstructured":"Zheng , W. , Feng , Y. , Huang , X. , and Mantooth , H . 2005. Ascend: Automatic bottom-up behavioral modeling tool for analog circuits . In Proceedings of the IEEE International Symposium on Circuits and Systems. 5186--5189 . Zheng, W., Feng, Y., Huang, X., and Mantooth, H. 2005. Ascend: Automatic bottom-up behavioral modeling tool for analog circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems. 5186--5189."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1970353.1970367","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1970353.1970367","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:53Z","timestamp":1750243973000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1970353.1970367"}},"subtitle":["A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models"],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":39,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2011,6]]}},"alternative-id":["10.1145\/1970353.1970367"],"URL":"https:\/\/doi.org\/10.1145\/1970353.1970367","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2011,6]]},"assertion":[{"value":"2010-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}