{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:27:48Z","timestamp":1750307268434,"version":"3.41.0"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2011,6,1]],"date-time":"2011-06-01T00:00:00Z","timestamp":1306886400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2011,6]]},"abstract":"<jats:p>Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.<\/jats:p>","DOI":"10.1145\/1970353.1970369","type":"journal-article","created":{"date-parts":[[2011,6,14]],"date-time":"2011-06-14T14:44:54Z","timestamp":1308062694000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications"],"prefix":"10.1145","volume":"16","author":[{"given":"Fady","family":"Abouzeid","sequence":"first","affiliation":[{"name":"STMicroelectronics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sylvain","family":"Clerc","sequence":"additional","affiliation":[{"name":"STMicroelectronics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabian","family":"Firmin","sequence":"additional","affiliation":[{"name":"STMicroelectronics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marc","family":"Renaudin","sequence":"additional","affiliation":[{"name":"TIMA Laboratory"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tiempo","family":"Sas","sequence":"additional","affiliation":[{"name":"TIMA Laboratory"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gilles","family":"Sicard","sequence":"additional","affiliation":[{"name":"TIMA Laboratory"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,6]]},"reference":[{"volume-title":"Proceedings of the Edition of the Faible Tension Faible Consommation (FTFC).","author":"Abouzeid F.","key":"e_1_2_1_1_1","unstructured":"Abouzeid , F. , Clerc , S. , Renaudin , M. , and Sicard , G . 2008. Design solutions for ultra-low voltage . In Proceedings of the Edition of the Faible Tension Faible Consommation (FTFC). Abouzeid, F., Clerc, S., Renaudin, M., and Sicard, G. 2008. Design solutions for ultra-low voltage. In Proceedings of the Edition of the Faible Tension Faible Consommation (FTFC)."},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design (ICCD\u201908)","author":"Bol D.","key":"e_1_2_1_2_1","unstructured":"Bol , D. , Ambroise , R. , Flandre , D. , and Legat , J . -D. 2008a. Analysis and minimization of practical energy in 45nm subthreshold logic circuits . In Proceedings of the IEEE International Conference on Computer Design (ICCD\u201908) . 294--300. Bol, D., Ambroise, R., Flandre, D., and Legat, J.-D. 2008a. Analysis and minimization of practical energy in 45nm subthreshold logic circuits. In Proceedings of the IEEE International Conference on Computer Design (ICCD\u201908). 294--300."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2008.75"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013265"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852162"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165579"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2008.4526473"},{"key":"e_1_2_1_8_1","first-page":"1","article-title":"Error control coding: Fundamentals and applications. IEE","volume":"132","author":"Darnell M.","year":"1985","unstructured":"Darnell , M. 1985 . Error control coding: Fundamentals and applications. IEE Proc. Comm. Radar Signal Process. F132 , 1 , 68. Darnell, M. 1985. Error control coding: Fundamentals and applications. IEE Proc. Comm. Radar Signal Process. F132, 1, 68.","journal-title":"Proc. Comm. Radar Signal Process."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the International Electro Conference.","author":"Graniello B.","year":"2005","unstructured":"Graniello , B. , Chavan , A. , Rodriguez , B. , and MacDonald , E. 2005 . Optimized circuit styles for subthreshold logic . In Proceedings of the International Electro Conference. Graniello, B., Chavan, A., Rodriguez, B., and MacDonald, E. 2005. Optimized circuit styles for subthreshold logic. In Proceedings of the International Electro Conference."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165653"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165660"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278656"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147022"},{"volume-title":"Proceedings of the Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).","author":"Masgonty J.-M.","key":"e_1_2_1_14_1","unstructured":"Masgonty , J.-M. , Cserveny , S. , Arm , C. , Pfister , P.-D. , and Piguet , C . 2001. Low-power low-voltage standard cell libraries with a limited number of cells . In Proceedings of the Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). Masgonty, J.-M., Cserveny, S., Arm, C., Pfister, P.-D., and Piguet, C. 2001. Low-power low-voltage standard cell libraries with a limited number of cells. In Proceedings of the Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.95"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.920822"},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the IEEE Austin Conference on Integrated Systems and Circuits.","author":"Sylvester D.","year":"2006","unstructured":"Sylvester , D. 2006 . Ic design strategies at ultra-low voltages . In Proceedings of the IEEE Austin Conference on Integrated Systems and Circuits. Sylvester, D. 2006. Ic design strategies at ultra-low voltages. In Proceedings of the IEEE Austin Conference on Integrated Systems and Circuits."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.911352"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.837945"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1970353.1970369","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1970353.1970369","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:53Z","timestamp":1750243973000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1970353.1970369"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":20,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2011,6]]}},"alternative-id":["10.1145\/1970353.1970369"],"URL":"https:\/\/doi.org\/10.1145\/1970353.1970369","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2011,6]]},"assertion":[{"value":"2010-01-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}