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Code Optim."],"published-print":{"date-parts":[[2011,7]]},"abstract":"<jats:p>The scalability of future Massively Parallel Processing (MPP) systems is being severely challenged by high failure rates. Current centralized Hard Disk Drive (HDD) checkpointing results in overhead of 25% or more at petascale. Since systems become more vulnerable as the node count keeps increasing, novel techniques that enable fast and frequent checkpointing are critical to the future exascale system implementation.<\/jats:p>\n          <jats:p>\n            In this work, we first introduce one of the emerging nonvolatile memory technologies,\n            <jats:italic>Phase-Change Random Access Memory<\/jats:italic>\n            (PCRAM), as a proper candidate of the fast checkpointing device. After a thorough analysis of MPP systems, failure rates and failure sources, we propose a PCRAM-based hybrid local\/global checkpointing mechanism which not only provides a faster checkpoint storage, but also boosts the effectiveness of other orthogonal techniques such as incremental checkpointing and background checkpointing. Three variant implementations of the PCRAM-based hybrid checkpointing are designed to be adopted at different stages and to offer a smooth transition from the conventional in-disk checkpointing to the instant in-memory approach. Analyzing the overhead by using a hybrid checkpointing performance model, we show the proposed approach only incurs less than 3% performance overhead on a projected exascale system.\n          <\/jats:p>","DOI":"10.1145\/1970386.1970387","type":"journal-article","created":{"date-parts":[[2011,6,21]],"date-time":"2011-06-21T13:47:26Z","timestamp":1308664046000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":46,"title":["Hybrid checkpointing using emerging nonvolatile memories for future exascale systems"],"prefix":"10.1145","volume":"8","author":[{"given":"Xiangyu","family":"Dong","sequence":"first","affiliation":[{"name":"Pennsylvania State University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Naveen","family":"Muralimanohar","sequence":"additional","affiliation":[{"name":"Hewlett-Packard Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Norman P.","family":"Jouppi","sequence":"additional","affiliation":[{"name":"Hewlett-Packard Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,6,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/762761.762787"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1345206.1345253"},{"key":"e_1_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Bronevetsky G. and Moody A. 2009. Scalable I\/O systems via node-local storage: Approaching 1 TB\/sec file I\/O. Tech. rep. LLNL-TR-415791 Lawrence Livermore National Laboratory.  Bronevetsky G. and Moody A. 2009. Scalable I\/O systems via node-local storage: Approaching 1 TB\/sec file I\/O. Tech. rep. LLNL-TR-415791 Lawrence Livermore National Laboratory.","DOI":"10.2172\/964079"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1177\/1094342009106189"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/214451.214456"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the 26th Annual Symposium on Fault Tolerant Computing. 370--379","author":"Chiueh T.-C.","unstructured":"Chiueh , T.-C. and Deng , P . 1996. Evaluation of checkpoint mechanisms for massively parallel machines . In Proceedings of the 26th Annual Symposium on Fault Tolerant Computing. 370--379 . Chiueh, T.-C. and Deng, P. 1996. Evaluation of checkpoint mechanisms for massively parallel machines. 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Tech. rep. LA-UR-07-7405 Los Alamos National Laboratory.  Grider G. Loncaric J. and Limpart D. 2007. Roadrunner system management report. Tech. rep. LA-UR-07-7405 Los Alamos National Laboratory."},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference. 474--616","author":"Hanzawa S.","year":"2007","unstructured":"Hanzawa , S. , Kitai , N. , Osada , K. , 2007 . A 512kb embedded phase change memory with 416kb\/s write throughput at 100&mu;a cell write current . In Proceedings of the IEEE International Solid-State Circuits Conference. 474--616 . Hanzawa, S., Kitai, N., Osada, K., et al. 2007. A 512kb embedded phase change memory with 416kb\/s write throughput at 100&mu;a cell write current. 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