{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:27:35Z","timestamp":1750307255267,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,5,2]],"date-time":"2011-05-02T00:00:00Z","timestamp":1304294400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,5,2]]},"DOI":"10.1145\/1973009.1973065","type":"proceedings-article","created":{"date-parts":[[2011,5,3]],"date-time":"2011-05-03T12:48:54Z","timestamp":1304426934000},"page":"277-282","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells"],"prefix":"10.1145","author":[{"given":"Nivard","family":"Aymerich","sequence":"first","affiliation":[{"name":"UPC Barcelona Tech, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shrikanth","family":"Ganapathy","sequence":"additional","affiliation":[{"name":"UPC Barcelona Tech, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonio","family":"Rubio","sequence":"additional","affiliation":[{"name":"UPC Barcelona Tech, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramon","family":"Canal","sequence":"additional","affiliation":[{"name":"UPC Barcelona Tech, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonio","family":"Gonz\u00e1lez","sequence":"additional","affiliation":[{"name":"Intel Labs &amp; UPC Barcelona Tech, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,5,2]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"International technology roadmap for semiconductors 2009 2009.  International technology roadmap for semiconductors 2009 2009."},{"key":"e_1_3_2_1_2_1","first-page":"390","volume-title":"ICCD 2009","author":"Bhoj A.","year":"2010","unstructured":"A. Bhoj and N. Jha . Pragmatic design of gated-diode FinFET DRAMs . In ICCD 2009 , pages 390 -- 397 . IEEE, 2010 . A. Bhoj and N. Jha. Pragmatic design of gated-diode FinFET DRAMs. In ICCD 2009, pages 390--397. IEEE, 2010."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2005.04.055"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPFA.2008.4588195"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"S. Drapatz G. Georgakos and D. Schmitt-Landsiedel. Impact of negative and positive bias temperature stress on 6T-SRAM cells. Advances in Radio Science-Kleinheubacher Berichte 7.  S. Drapatz G. Georgakos and D. Schmitt-Landsiedel. Impact of negative and positive bias temperature stress on 6T-SRAM cells. Advances in Radio Science-Kleinheubacher Berichte 7.","DOI":"10.5194\/ars-7-191-2009"},{"key":"e_1_3_2_1_6_1","volume-title":"AC NBTI studied in the 1 Hz 2 GHz range on dedicated on-chip CMOS circuits","author":"Kaczer B.","year":"2006","unstructured":"B. Kaczer , A. Nackaerts , S. Demuynck , R. Rodriguez , and M. Nafria . AC NBTI studied in the 1 Hz 2 GHz range on dedicated on-chip CMOS circuits . 2006 . B. Kaczer, A. Nackaerts, S. Demuynck, R. Rodriguez, and M. Nafria. AC NBTI studied in the 1 Hz 2 GHz range on dedicated on-chip CMOS circuits. 2006."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.896317"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1509633.1509709"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.12"},{"key":"e_1_3_2_1_10_1","first-page":"450","volume-title":"Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on","author":"Lorenzo M.","year":"2009","unstructured":"M. Lorenzo , W. Tan , A. Ballesil , and L. Alarcon . Experimental analysis of read related transistors' gate width sizing effects on the 3T1D DRAM access time curve . In Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on , pages 450 -- 454 . IEEE, 2009 . M. Lorenzo, W. Tan, A. Ballesil, and L. Alarcon. Experimental analysis of read related transistors' gate width sizing effects on the 3T1D DRAM access time curve. In Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on, pages 450--454. IEEE, 2009."},{"key":"e_1_3_2_1_11_1","first-page":"398","volume-title":"Computer Design, 2009. ICCD 2009. IEEE International Conference on","author":"Lovin K.","year":"2010","unstructured":"K. Lovin , B. Lee , X. Liang , D. Brooks , and G. Wei . Empirical performance models for 3T1D memories . In Computer Design, 2009. ICCD 2009. IEEE International Conference on , pages 398 -- 403 . IEEE, 2010 . K. Lovin, B. Lee, X. Liang, D. Brooks, and G. Wei. Empirical performance models for 3T1D memories. In Computer Design, 2009. ICCD 2009. IEEE International Conference on, pages 398--403. IEEE, 2010."},{"key":"e_1_3_2_1_12_1","first-page":"184","volume-title":"VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on","author":"Luk W.","year":"2007","unstructured":"W. Luk , J. Cai , R. Dennard , M. Immediato , and S. Kosonocky . A 3-transistor DRAM cell with gated diode for enhanced speed and retention time . In VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on , pages 184 -- 185 . IEEE, 2007 . W. Luk, J. Cai, R. Dennard, M. Immediato, and S. Kosonocky. A 3-transistor DRAM cell with gated diode for enhanced speed and retention time. In VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on, pages 184--185. IEEE, 2007."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035535"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"issue":"1","key":"e_1_3_2_1_15_1","first-page":"3","article-title":"VARIUS: A model of process variation and resulting timing errors for microarchitects. Semiconductor Manufacturing","volume":"21","author":"Sarangi S.","year":"2008","unstructured":"S. Sarangi , B. Greskamp , R. Teodorescu , J. Nakano , A. Tiwari , and J. Torrellas . VARIUS: A model of process variation and resulting timing errors for microarchitects. Semiconductor Manufacturing , IEEE Transactions on , 21 ( 1 ): 3 -- 13 , 2008 . S. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas. VARIUS: A model of process variation and resulting timing errors for microarchitects. Semiconductor Manufacturing, IEEE Transactions on, 21(1):3--13, 2008.","journal-title":"IEEE Transactions on"}],"event":{"name":"GLSVLSI '11: Great Lakes Symposium on VLSI 2011","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Lausanne Switzerland","acronym":"GLSVLSI '11"},"container-title":["Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1973009.1973065","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1973009.1973065","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:23Z","timestamp":1750243943000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1973009.1973065"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5,2]]},"references-count":15,"alternative-id":["10.1145\/1973009.1973065","10.1145\/1973009"],"URL":"https:\/\/doi.org\/10.1145\/1973009.1973065","relation":{},"subject":[],"published":{"date-parts":[[2011,5,2]]},"assertion":[{"value":"2011-05-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}