{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:06:43Z","timestamp":1759147603541,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,5,2]],"date-time":"2011-05-02T00:00:00Z","timestamp":1304294400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,5,2]]},"DOI":"10.1145\/1973009.1973074","type":"proceedings-article","created":{"date-parts":[[2011,5,3]],"date-time":"2011-05-03T12:48:54Z","timestamp":1304426934000},"page":"325-330","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Circuit design of a dual-versioning L1 data cache for optimistic concurrency"],"prefix":"10.1145","author":[{"given":"Azam","family":"Seyedi","sequence":"first","affiliation":[{"name":"BSC - Microsoft Research Centre & Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}]},{"given":"Adri\u00e0","family":"Armejach","sequence":"additional","affiliation":[{"name":"BSC - Microsoft Research Centre & Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}]},{"given":"Adri\u00e1n","family":"Cristal","sequence":"additional","affiliation":[{"name":"BSC - Microsoft Research Centre & IIIA - Artificial Intelligence Research Institute CSIC, Barcelona, Spain"}]},{"given":"Osman S.","family":"Unsal","sequence":"additional","affiliation":[{"name":"BSC - Microsoft Research Centre, Barcelona, Spain"}]},{"given":"Ibrahim","family":"Hur","sequence":"additional","affiliation":[{"name":"BSC - Microsoft Research Centre, Barcelona, Spain"}]},{"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[{"name":"BSC - Microsoft Research Centre & Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}]}],"member":"320","published-online":{"date-parts":[[2011,5,2]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Predictive technology model. http:\/\/ptm.asu.edu\/.  Predictive technology model. http:\/\/ptm.asu.edu\/."},{"key":"e_1_3_2_1_2_1","unstructured":"The Electric VLSI Design System. http:\/\/www.staticfreesoft.com.  The Electric VLSI Design System. http:\/\/www.staticfreesoft.com."},{"key":"e_1_3_2_1_3_1","volume-title":"IBM","author":"Operation RAM","year":"1997","unstructured":"Understanding Static RAM Operation . Technical Report IBM Application Notes , IBM , 1997 . Understanding Static RAM Operation. Technical Report IBM Application Notes, IBM, 1997."},{"key":"e_1_3_2_1_6_1","volume-title":"IISWC","author":"Cao C.","year":"2008","unstructured":"C. Cao Minh et al. STAMP: Stanford transactional applications for multi-processing . In IISWC , 2008 . C. Cao Minh et al. STAMP: Stanford transactional applications for multi-processing. In IISWC, 2008."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.896693"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.145"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01728-5","volume-title":"Transactional Memory","author":"Harris T.","year":"2010","unstructured":"T. Harris Transactional Memory , 2 nd edition. Synthesis Lectures on Computer Architecture , 2010 . T. Harris et al. Transactional Memory, 2nd edition. Synthesis Lectures on Computer Architecture, 2010.","edition":"2"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.795218"},{"key":"e_1_3_2_1_11_1","volume-title":"ISSCC","author":"Pille J.","year":"2010","unstructured":"J. Pille A 32kB 2R\/1W L1 data cache in 45nm SOI technology for the POWER7TM processor . In ISSCC , 2010 . J. Pille et al. A 32kB 2R\/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. In ISSCC, 2010."},{"key":"e_1_3_2_1_12_1","volume-title":"Digital integrated circuits - A design perspective","author":"Rabaey J. M.","year":"2004","unstructured":"J. M. Rabaey Digital integrated circuits - A design perspective . Prentice Hall , 2 nd edition, 2004 . J. M. Rabaey et al. Digital integrated circuits - A design perspective. Prentice Hall, 2nd edition, 2004.","edition":"2"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/563998.564036"},{"key":"e_1_3_2_1_15_1","volume-title":"IEEE JSSC","author":"Wang Y.","year":"2008","unstructured":"Y. Wang A 1. 1 GHz 12 \u03bcA\/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications . IEEE JSSC , 2008 . Y. Wang et al. A 1.1 GHz 12 \u03bcA\/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. IEEE JSSC, 2008."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.687996"},{"key":"e_1_3_2_1_17_1","volume-title":"Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology. Master's thesis","author":"Yeknami A. F.","year":"2008","unstructured":"A. F. Yeknami . Design and Evaluation of A Low-Voltage , Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology. Master's thesis , 2008 . Link\u00f6ping University , Sweden . A. F. Yeknami. Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology. Master's thesis, 2008. Link\u00f6ping University, Sweden."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346204"},{"key":"e_1_3_2_1_19_1","volume":"200","author":"Yu Y.","unstructured":"Y. Yu Multi-valued static random access memory (SRAM) cell with single-electron and MOSFET hybrid circuit. Electronics Letters , 200 5. Y. Yu et al. Multi-valued static random access memory (SRAM) cell with single-electron and MOSFET hybrid circuit. Electronics Letters, 2005.","journal-title":"Electronics Letters"}],"event":{"name":"GLSVLSI '11: Great Lakes Symposium on VLSI 2011","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Lausanne Switzerland","acronym":"GLSVLSI '11"},"container-title":["Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1973009.1973074","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1973009.1973074","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:23Z","timestamp":1750243943000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1973009.1973074"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5,2]]},"references-count":16,"alternative-id":["10.1145\/1973009.1973074","10.1145\/1973009"],"URL":"https:\/\/doi.org\/10.1145\/1973009.1973074","relation":{},"subject":[],"published":{"date-parts":[[2011,5,2]]},"assertion":[{"value":"2011-05-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}