{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:38:17Z","timestamp":1761647897344,"version":"3.41.0"},"reference-count":55,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2011,10,1]],"date-time":"2011-10-01T00:00:00Z","timestamp":1317427200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000104","name":"National Aeronautics and Space Administration","doi-asserted-by":"publisher","award":["NNA04CL07A"],"award-info":[{"award-number":["NNA04CL07A"]}],"id":[{"id":"10.13039\/100000104","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Comput. Surv."],"published-print":{"date-parts":[[2011,10]]},"abstract":"<jats:p>The capabilities of current fault-handling techniques for Field Programmable Gate Arrays (FPGAs) develop a descriptive classification ranging from simple passive techniques to robust dynamic methods. Fault-handling methods not requiring modification of the FPGA device architecture or user intervention to recover from faults are examined and evaluated against overhead-based and sustainability-based performance metrics such as additional resource requirements, throughput reduction, fault capacity, and fault coverage. This classification alongside these performance metrics forms a standard for confident comparisons.<\/jats:p>","DOI":"10.1145\/1978802.1978810","type":"journal-article","created":{"date-parts":[[2011,10,18]],"date-time":"2011-10-18T13:01:58Z","timestamp":1318942918000},"page":"1-30","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":26,"title":["Progress in autonomous fault recovery of field programmable gate arrays"],"prefix":"10.1145","volume":"43","author":[{"given":"Matthew G.","family":"Parris","sequence":"first","affiliation":[{"name":"NASA Kennedy Space Center, FL"}]},{"given":"Carthik A.","family":"Sharma","sequence":"additional","affiliation":[{"name":"University of Central Florida, FL"}]},{"given":"Ronald F.","family":"Demara","sequence":"additional","affiliation":[{"name":"University of Central Florida, FL"}]}],"member":"320","published-online":{"date-parts":[[2011,10,18]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.837989"},{"key":"e_1_2_1_2_1","unstructured":"Actel. 2005. Radiation-Hardened FPGAs datasheet. http:\/\/www.actel.com\/documents\/RadHard_DS.pdf. Actel. 2005. Radiation-Hardened FPGAs datasheet. http:\/\/www.actel.com\/documents\/RadHard_DS.pdf."},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Adell P. and Allen G. 2008. Assessing and mitigating radiation effects in Xilinx FPGAs. JPL Publ. 08-09. Adell P. and Allen G. 2008. Assessing and mitigating radiation effects in Xilinx FPGAs. JPL Publ. 08-09.","DOI":"10.1109\/RADECS.2008.5782755"},{"key":"e_1_2_1_4_1","unstructured":"Altera. 2009. Stratix IV device handbook. http:\/\/www.altera.com\/literature\/hb\/stratix-iv\/stratix4_handbook.pdf. Altera. 2009. Stratix IV device handbook. http:\/\/www.altera.com\/literature\/hb\/stratix-iv\/stratix4_handbook.pdf."},{"key":"e_1_2_1_5_1","unstructured":"Atmel. 2007. Rad hard reprogrammable FPGA ATF280E. Atmel datasheet 7750. Atmel. 2007. Rad hard reprogrammable FPGA ATF280E. Atmel datasheet 7750."},{"volume-title":"Proceedings of the 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines. 134--143","author":"Babb J.","key":"e_1_2_1_6_1"},{"volume-title":"Proceedings of the Military and Aerospace Programmable Logic Devices (MAPLD) Workshop.","author":"Baldacci S.","key":"e_1_2_1_7_1"},{"key":"e_1_2_1_8_1","unstructured":"Bridgford B. Carmichael C. and Tseng C. W. 2008. Single-event upset mitigation selection guide. Xilinx Application Note 987. Bridgford B. Carmichael C. and Tseng C. W. 2008. Single-event upset mitigation selection guide. Xilinx Application Note 987."},{"key":"e_1_2_1_9_1","unstructured":"Carmichael C. Caffrey M. and Salazar A. 2000. Correcting single-event upsets through virtex partial configuration. Xilinx Application Note 216. Carmichael C. Caffrey M. and Salazar A. 2000. Correcting single-event upsets through virtex partial configuration. Xilinx Application Note 216."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1142155.1142167"},{"volume-title":"Proceedings of the 27th Annual International Symposium on Fault-Tolerant Computing. 339--348","author":"Dave B. P.","key":"e_1_2_1_11_1"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/EH.2005.11"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1088\/1009-1963\/16\/12\/034"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.801609"},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. 173--176","author":"Dutt S.","key":"e_1_2_1_15_1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.906992"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008365019152"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.891102"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/1009387.1010282"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001141"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.656073"},{"key":"e_1_2_1_22_1","unstructured":"Huang W.-J. Mitra S. and McCluskey E. J. 2001. Fast run-time fault location in dependable FPGAs. CRC Tech. rep. 01-5 Center for Reliable Computing Department of Electrical Engineering and Computer Science Stanford University. May. Huang W.-J. Mitra S. and McCluskey E. J. 2001. Fast run-time fault location in dependable FPGAs. CRC Tech. rep. 01-5 Center for Reliable Computing Department of Electrical Engineering and Computer Science Stanford University. May."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/258305.258333"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1160056"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/24.914547"},{"volume-title":"Proceedings of the IEEE Aerospace Conference. U. D. Patel Ed., 1--10","author":"Kizhner S.","key":"e_1_2_1_26_1"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.678870"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329205"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/838237.838725"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.62.0200"},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications. 1--6.","author":"Lysaght P.","key":"e_1_2_1_31_1"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10710-008-9058-x"},{"key":"e_1_2_1_33_1","unstructured":"Miller J. F. Thomson P. and Fogarty T. 1997. Designing electronic circuits using evolutionary algorithms. Arithmetic circuits: A case study. In Genetic Algorithms and Evolution Strategies in Engineering and Computer Science D. Quagliarella J. Periaux C. Poloni and G. Winter Eds. Wiley 105--131. Miller J. F. Thomson P. and Fogarty T. 1997. Designing electronic circuits using evolutionary algorithms. Arithmetic circuits: A case study. In Genetic Algorithms and Evolution Strategies in Engineering and Computer Science D. Quagliarella J. Periaux C. Poloni and G. Winter Eds. Wiley 105--131."},{"key":"e_1_2_1_34_1","doi-asserted-by":"crossref","unstructured":"Mitchell M. 1996. An Introduction to Genetic Algorithms. MIT Press Cambridge MA. Mitchell M. 1996. An Introduction to Genetic Algorithms. MIT Press Cambridge MA.","DOI":"10.7551\/mitpress\/3927.001.0001"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.18"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/RECONF.2006.307760"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1010080629099"},{"key":"e_1_2_1_38_1","unstructured":"Parris M. G. 2008. Optimizing dynamic logic realizations for partial reconfiguration of field programmable gate arrays. Masters thesis School of Electrical Engineering and Computer Science University of Central Florida. Parris M. G. 2008. Optimizing dynamic logic realizations for partial reconfiguration of field programmable gate arrays. Masters thesis School of Electrical Engineering and Computer Science University of Central Florida."},{"key":"e_1_2_1_39_1","first-page":"8","article-title":"FPGAs on mars","volume":"50","author":"Ratter D.","year":"2004","journal-title":"Xcell J."},{"key":"e_1_2_1_40_1","unstructured":"Roosta R. 2004. A comparison of radiation-hard and radiation-tolerant FPGAs for space applications. NASA Electronic Parts and Packaging (NEPP) Program JPL D-31228. Roosta R. 2004. A comparison of radiation-hard and radiation-tolerant FPGAs for space applications. NASA Electronic Parts and Packaging (NEPP) Program JPL D-31228."},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2006.3"},{"key":"e_1_2_1_42_1","doi-asserted-by":"crossref","unstructured":"Schwefel H.-P. and Rudolph G. 1995. Contemporary evolution strategies. In Advances in Artificial Life. Springer 891--907. Schwefel H.-P. and Rudolph G. 1995. Contemporary evolution strategies. In Advances in Artificial Life. Springer 891--907.","DOI":"10.1007\/3-540-59496-5_351"},{"volume-title":"Proceedings of the HiPC Workshop on Soft Computing. 81--89","author":"Shanthi A. P.","key":"e_1_2_1_43_1"},{"key":"e_1_2_1_44_1","unstructured":"Sharma C. A. 2008. Sustainable fault-handling of reconfigurable logic using throughput-driven assessment. Doctoral dissertation School of Electrical Engineering and Computer Science University of Central Florida. Sharma C. A. 2008. Sustainable fault-handling of reconfigurable logic using throughput-driven assessment. Doctoral dissertation School of Electrical Engineering and Computer Science University of Central Florida."},{"key":"e_1_2_1_45_1","article-title":"Self-healing reconfigurable logic using autonomous group testing. ACM","author":"Sharma C. A.","year":"2007","journal-title":"Trans. Auton. Adapt. Syst."},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.231341"},{"key":"e_1_2_1_47_1","unstructured":"Vigander S. 2001. Evolutionary fault repair of electronics in space applications. Masters thesis Department of Computer and Information Science Norwegian University of Science and Technology (NTNU) Trondheim Norway. 50. Vigander S. 2001. Evolutionary fault repair of electronics in space applications. Masters thesis Department of Computer and Information Science Norwegian University of Science and Technology (NTNU) Trondheim Norway. 50."},{"volume-title":"Proceedings of the 20th Digital Avionics Systems.","author":"Wells B. E.","key":"e_1_2_1_48_1"},{"volume-title":"Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. 133--142","author":"Wirthlin M.","key":"e_1_2_1_49_1"},{"key":"e_1_2_1_50_1","unstructured":"Xilinx. 2007. Virtex-4 family overview. Xilinx Data Sheet 112. Xilinx. 2007. Virtex-4 family overview. Xilinx Data Sheet 112."},{"key":"e_1_2_1_51_1","unstructured":"Xilinx. 2008. Radiation-Tolerant virtex-4 QPro-V family overview. Xilinx Data Sheet 653. Xilinx. 2008. Radiation-Tolerant virtex-4 QPro-V family overview. Xilinx Data Sheet 653."},{"key":"e_1_2_1_52_1","unstructured":"Xilinx. 2009. Virtex-4 FPGA configuration user guide. Xilinx User Guide 071. Xilinx. 2009. Virtex-4 FPGA configuration user guide. Xilinx User Guide 071."},{"key":"e_1_2_1_53_1","unstructured":"Yang S. 1991. Logic synthesis and optimization benchmarks user guide version 3.0. Tech. rep. Microelectronics Center of North Carolina. Yang S. 1991. Logic synthesis and optimization benchmarks user guide version 3.0. Tech. rep. Microelectronics Center of North Carolina."},{"volume-title":"Proceedings of the IEEE Nuclear and Space Radiation Effects Conference.","author":"Yui C. C.","key":"e_1_2_1_54_1"},{"volume-title":"Proceedings of the IEEE Systems Readiness Technology Conference. 690--696","author":"Zhang K.","key":"e_1_2_1_55_1"}],"container-title":["ACM Computing Surveys"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1978802.1978810","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1978802.1978810","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:59:38Z","timestamp":1750244378000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1978802.1978810"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":55,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2011,10]]}},"alternative-id":["10.1145\/1978802.1978810"],"URL":"https:\/\/doi.org\/10.1145\/1978802.1978810","relation":{},"ISSN":["0360-0300","1557-7341"],"issn-type":[{"type":"print","value":"0360-0300"},{"type":"electronic","value":"1557-7341"}],"subject":[],"published":{"date-parts":[[2011,10]]},"assertion":[{"value":"2009-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-10-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}