{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T12:17:54Z","timestamp":1767183474055,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,5,1]],"date-time":"2011-05-01T00:00:00Z","timestamp":1304208000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0810408CCF-0702539"],"award-info":[{"award-number":["CCF-0810408CCF-0702539"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["1817.001"],"award-info":[{"award-number":["1817.001"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1145\/1999946.1999976","type":"proceedings-article","created":{"date-parts":[[2011,6,28]],"date-time":"2011-06-28T17:34:50Z","timestamp":1309282490000},"page":"185-192","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Link pipelining strategies for an application-specific asynchronous NoC"],"prefix":"10.1145","author":[{"given":"Daniel","family":"Gebhardt","sequence":"first","affiliation":[{"name":"University of Utah"}]},{"given":"Junbok","family":"You","sequence":"additional","affiliation":[{"name":"University of Utah"}]},{"given":"Kenneth S.","family":"Stevens","sequence":"additional","affiliation":[{"name":"University of Utah"}]}],"member":"320","published-online":{"date-parts":[[2011,5]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"139","article-title":"Physical implementation of the dspin network-on-chip in the faust architecture","author":"Panades I. M.","year":"2008","unstructured":"I. M. Panades , F. Clermidy , P. Vivet , and A. Greiner , \" Physical implementation of the dspin network-on-chip in the faust architecture ,\" in Proc. Int'l Symp. on Networks-on-Chips , 2008 , pp. 139 -- 148 . I. M. Panades, F. Clermidy, P. Vivet, and A. Greiner, \"Physical implementation of the dspin network-on-chip in the faust architecture,\" in Proc. Int'l Symp. on Networks-on-Chips, 2008, pp. 139--148.","journal-title":"Proc. Int'l Symp. on Networks-on-Chips"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1109\/MM.2007.77"},{"key":"e_1_3_2_1_3_1","volume-title":"An OOP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip.\" in Proc. of Int'l Symp. on System-on-Chip","author":"Bjerregaard T.","year":"2005","unstructured":"T. Bjerregaard , S. Mahadevan , R. G. Olsen , and J. Spars\u00f8 , \" An OOP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip.\" in Proc. of Int'l Symp. on System-on-Chip , 2005 . T. Bjerregaard, S. Mahadevan, R. G. Olsen, and J. Spars\u00f8, \"An OOP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip.\" in Proc. of Int'l Symp. on System-on-Chip, 2005."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1109\/ISCA.2008.14"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.1016\/j.vlsi.2007.12.002"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_6_1","DOI":"10.1145\/1120725.1121009"},{"key":"e_1_3_2_1_7_1","first-page":"151","article-title":"Elastic-buffer flow control for on-chip networks","author":"Michelogiannakis G.","year":"2009","unstructured":"G. Michelogiannakis , J. Balfour , and W. Dally , \" Elastic-buffer flow control for on-chip networks ,\" in Proc. Int'l Symp. on High Performance Computer Architecture , 2009 , pp. 151 -- 162 . G. Michelogiannakis, J. Balfour, and W. Dally, \"Elastic-buffer flow control for on-chip networks,\" in Proc. Int'l Symp. on High Performance Computer Architecture, 2009, pp. 151--162.","journal-title":"Proc. Int'l Symp. on High Performance Computer Architecture"},{"key":"e_1_3_2_1_8_1","first-page":"455","volume-title":"IEEE","author":"You J.","year":"2010","unstructured":"J. You , D. Gebhardt , and K. S. Stevens , \" Bandwidth Optimization in Asynchronous NoCs by Customizing Link Wire Length,\" in International Conference on Computer Design . IEEE , Oct 2010 , pp. 455 -- 461 . J. You, D. Gebhardt, and K. S. Stevens, \"Bandwidth Optimization in Asynchronous NoCs by Customizing Link Wire Length,\" in International Conference on Computer Design. IEEE, Oct 2010, pp. 455--461."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1145\/1669112.1669145"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.1049\/ip-cdt:20050067"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_11_1","DOI":"10.1109\/TCAD.2009.2013273"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.1145\/1233501.1233573"},{"key":"e_1_3_2_1_13_1","volume-title":"Network delays and link capacities in application-specific wormhole noes,\" VLSI Design","author":"Guz Z.","year":"2007","unstructured":"Z. Guz , I. Walter , E. Bolotin , I. Cidon , R. Ginosar , and A. Kolodny , \" Network delays and link capacities in application-specific wormhole noes,\" VLSI Design , vol. 2007 , 2007 . Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, \"Network delays and link capacities in application-specific wormhole noes,\" VLSI Design, vol. 2007, 2007."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1109\/MM.2004.1268991"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1109\/MM.2002.1044296"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1109\/DATE.2005.36"},{"key":"e_1_3_2_1_17_1","volume-title":"Digest of Technical Papers","author":"Lattard D.","year":"2007","unstructured":"D. Lattard , E. Beigne , C. Bernard , C. Bour , F. Clermidy , Y. Durand , J. Durupt , D. Varreau , P. Vivet , P. Penard , A. Bouffier , and F. Berens , \" A telecom baseband circuit based on an asynchronous network-on-chip,\" Solid-State Circuits Conference , Digest of Technical Papers , Feb. 2007 . D. Lattard, E. Beigne, C. Bernard, C. Bour, F. Clermidy, Y. Durand, J. Durupt, D. Varreau, P. Vivet, P. Penard, A. Bouffier, and F. Berens, \"A telecom baseband circuit based on an asynchronous network-on-chip,\" Solid-State Circuits Conference, Digest of Technical Papers, Feb. 2007."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.1109\/ASYNC.2005.10"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_19_1","DOI":"10.1016\/j.vlsi.2008.03.001"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_20_1","DOI":"10.1109\/NOCS.2010.14"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1109\/NOCS.2010.21"},{"key":"e_1_3_2_1_22_1","first-page":"1","article-title":"Mapping of mpeg-4 decoding on a flexible architecture platform","author":"Tol E. B. V. D.","year":"2002","unstructured":"E. B. V. D. Tol and E. G. T. Jaspers , \" Mapping of mpeg-4 decoding on a flexible architecture platform ,\" in Media Processors , 2002 , pp. 1 -- 13 . E. B. V. D. Tol and E. G. T. Jaspers, \"Mapping of mpeg-4 decoding on a flexible architecture platform,\" in Media Processors, 2002, pp. 1--13.","journal-title":"Media Processors"},{"key":"e_1_3_2_1_23_1","first-page":"423","article-title":"Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration","author":"Kahng A.","year":"2009","unstructured":"A. Kahng , B. Li , L.-S. Peh , and K. Samadi , \" Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration ,\" in DATE , April 2009 , pp. 423 -- 428 . A. Kahng, B. Li, L.-S. Peh, and K. Samadi, \"Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration,\" in DATE, April 2009, pp. 423--428.","journal-title":"DATE"},{"key":"e_1_3_2_1_24_1","volume-title":"International Conference on Data Engineering","author":"Wang M.","year":"2002","unstructured":"M. Wang , T. Madhyastha , N. H. Chan , S. Papadimitriou , and C. Faloutsos , \" Data mining meets performance evaluation: fast algorithms for modeling bursty traffic,\" in Proc . International Conference on Data Engineering , 2002 . M. Wang, T. Madhyastha, N. H. Chan, S. Papadimitriou, and C. Faloutsos, \"Data mining meets performance evaluation: fast algorithms for modeling bursty traffic,\" in Proc. International Conference on Data Engineering, 2002."}],"event":{"sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","SIGARCH ACM Special Interest Group on Computer Architecture"],"acronym":"NOCS'11","name":"NOCS'11: International Symposium on Networks-on-Chips","location":"Pittsburgh Pennsylvania"},"container-title":["Proceedings of the Fifth ACM\/IEEE International Symposium on Networks-on-Chip"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1999946.1999976","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1999946.1999976","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:05:51Z","timestamp":1750244751000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1999946.1999976"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":24,"alternative-id":["10.1145\/1999946.1999976","10.1145\/1999946"],"URL":"https:\/\/doi.org\/10.1145\/1999946.1999976","relation":{},"subject":[],"published":{"date-parts":[[2011,5]]},"assertion":[{"value":"2011-05-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}