{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:47:10Z","timestamp":1772164030153,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,6,4]],"date-time":"2011-06-04T00:00:00Z","timestamp":1307145600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,6,4]]},"DOI":"10.1145\/2000064.2000079","type":"proceedings-article","created":{"date-parts":[[2011,6,28]],"date-time":"2011-06-28T13:34:50Z","timestamp":1309268090000},"page":"117-128","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":25,"title":["OUTRIDER"],"prefix":"10.1145","author":[{"given":"Neal Clayton","family":"Crago","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjay Jeram","family":"Patel","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,6,4]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.1"},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/165939.165952"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.49"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555814"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263597"},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195534"},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/327010.327117"},{"key":"e_1_3_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.20"},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/527072.822633"},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555774"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250683"},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/139669.140380"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379250"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/377792.377856"},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"e_1_3_2_2_17_1"},{"key":"e_1_3_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.13"},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.956093"},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1400112.1400113"},{"key":"e_1_3_2_2_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/646665.698932"},{"key":"e_1_3_2_2_22_1","first-page":"56","volume-title":"IEEE International Solid-State Circuits Conference","author":"Rusu S.","year":"2009","unstructured":"S. Rusu , S. Tam , H. Muljono , J. Stinson , D. Ayers , J. Chang , R. Varada , M. Ratta , and S. Kottapalli . A 45nm 8-core enterprise Xeon processor . In IEEE International Solid-State Circuits Conference , pages 56 -- 57 , 2009 . S. Rusu, S. Tam, H. Muljono, J. Stinson, D. Ayers, J. Chang, R. Varada, M. Ratta, and S. Kottapalli. A 45nm 8-core enterprise Xeon processor. In IEEE International Solid-State Circuits Conference, pages 56--57, 2009."},{"key":"e_1_3_2_2_23_1","first-page":"98","volume-title":"IEEE International Solid-State Circuits Conference","author":"Shin J.","year":"2010","unstructured":"J. Shin , K. Tam , D. Huang , B. Petrick , H. Pham , C. Hwang , H. Li , A. Smith , T. Johnson , F. Schumacher , D. Greenhill , A. Leon , and A. Strong . A 40nm 16-core 128-thread CMT SPARC SoC processor . In IEEE International Solid-State Circuits Conference , pages 98 -- 99 , 2010 . J. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson, F. Schumacher, D. Greenhill, A. Leon, and A. Strong. A 40nm 16-core 128-thread CMT SPARC SoC processor. In IEEE International Solid-State Circuits Conference, pages 98--99, 2010."},{"key":"e_1_3_2_2_24_1","first-page":"112","volume-title":"Proceedings of the 9th Annual Symposium on Computer Architecture","author":"Smith J. E.","year":"1982","unstructured":"J. E. Smith . Decoupled access\/execute computer architectures. In Proceedings of the 9th Annual Symposium on Computer Architecture , pages 112 -- 119 , 1982 . J. E. Smith. Decoupled access\/execute computer architectures. In Proceedings of the 9th Annual Symposium on Computer Architecture, pages 112--119, 1982."},{"key":"e_1_3_2_2_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/36206.36203"},{"key":"e_1_3_2_2_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/224170.224301"},{"key":"e_1_3_2_2_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224449"},{"key":"e_1_3_2_2_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/144953.145800"},{"key":"e_1_3_2_2_29_1","first-page":"1","volume-title":"IEEE 16th International Symposium on High-performance Computer Architecture","author":"Ware M.","year":"2010","unstructured":"M. Ware , K. Rajamani , M. Floyd , B. Brock , J. Rubio , F. Rawson , and J. Carter . Architecting for power management: The IBM POWER7 approach . In IEEE 16th International Symposium on High-performance Computer Architecture , pages 1 -- 11 , 2010 . M. Ware, K. Rajamani, M. Floyd, B. Brock, J. Rubio, F. Rawson, and J. Carter. Architecting for power management: The IBM POWER7 approach. In IEEE 16th International Symposium on High-performance Computer Architecture, pages 1--11, 2010."}],"event":{"name":"ISCA '11: The 38th Annual International Symposium on Computer Architecture","location":"San Jose California USA","acronym":"ISCA '11","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS"]},"container-title":["Proceedings of the 38th annual international symposium on Computer architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2000064.2000079","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2000064.2000079","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:56Z","timestamp":1750225736000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2000064.2000079"}},"subtitle":["efficient memory latency tolerance with decoupled strands"],"short-title":[],"issued":{"date-parts":[[2011,6,4]]},"references-count":29,"alternative-id":["10.1145\/2000064.2000079","10.1145\/2000064"],"URL":"https:\/\/doi.org\/10.1145\/2000064.2000079","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2024723.2000079","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2011,6,4]]},"assertion":[{"value":"2011-06-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}