{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,15]],"date-time":"2026-07-15T15:23:41Z","timestamp":1784129021407,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,6,4]],"date-time":"2011-06-04T00:00:00Z","timestamp":1307145600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,6,4]]},"DOI":"10.1145\/2000064.2000108","type":"proceedings-article","created":{"date-parts":[[2011,6,28]],"date-time":"2011-06-28T13:34:50Z","timestamp":1309268090000},"page":"365-376","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":527,"title":["Dark silicon and the end of multicore scaling"],"prefix":"10.1145","author":[{"given":"Hadi","family":"Esmaeilzadeh","sequence":"first","affiliation":[{"name":"University of Washington, Seattle, WA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Emily","family":"Blem","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Renee","family":"St. Amant","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Karthikeyan","family":"Sankaralingam","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Doug","family":"Burger","sequence":"additional","affiliation":[{"name":"Microsoft Research, Seattle, WA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2011,6,4]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815967"},{"key":"e_1_3_2_2_3_1","volume-title":"ISPASS '09","author":"Bakhoda A.","unstructured":"A. Bakhoda , G. L. Yuan , W. W. L. Fung , H. Wong , and T. M. Aamodt . Analyzing CUDA workloads using a detailed GPU simulator . In ISPASS '09 . A. Bakhoda, G. L. Yuan, W. W. L. Fung, H. Wong, and T. M. Aamodt. Analyzing CUDA workloads using a detailed GPU simulator. In ISPASS '09."},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306793"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278667"},{"key":"e_1_3_2_2_7_1","volume-title":"Automation and Test (VLSI-DAT)","author":"Borkar S.","year":"2010","unstructured":"S. Borkar . The exascale challenge. Keynote at International Symposium on VLSI Design , Automation and Test (VLSI-DAT) , 2010 . S. Borkar. The exascale challenge. Keynote at International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2010."},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.18"},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.36"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950402"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2009.4"},{"key":"e_1_3_2_2_14_1","volume-title":"MoBS '09","author":"Hempstead M.","unstructured":"M. Hempstead , G.-Y. Wei , and D. Brooks . Navigo: An early-stage model to study power-contrained architectures and specialization . In MoBS '09 . M. Hempstead, G.-Y. Wei, and D. Brooks. Navigo: An early-stage model to study power-contrained architectures and specialization. In MoBS '09."},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"e_1_3_2_2_16_1","volume-title":"IEDM '05","author":"Horowitz M.","unstructured":"M. Horowitz , E. Alon , D. Patil , S. Naffziger , R. Kumar , and K. Bernstein . Scaling, power, and the future of CMOS . In IEDM '05 . M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein. Scaling, power, and the future of CMOS. In IEDM '05."},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250686"},{"key":"e_1_3_2_2_18_1","volume-title":"2010 update","author":"ITRS.","year":"2011","unstructured":"ITRS. International technology roadmap for semiconductors , 2010 update , 2011 . URL http:\/\/www.itrs.net. ITRS. International technology roadmap for semiconductors, 2010 update, 2011. URL http:\/\/www.itrs.net."},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/1331699.1331733"},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-92295-7_13"},{"key":"e_1_3_2_2_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816021"},{"key":"e_1_3_2_2_22_1","volume-title":"ALTA '08","author":"Loh G.","unstructured":"G. Loh . The cost of uncore in throughput-oriented many-core processors . In ALTA '08 . G. Loh. The cost of uncore in throughput-oriented many-core processors. In ALTA '08."},{"key":"e_1_3_2_2_23_1","volume-title":"April","author":"Moore G. E.","year":"1965","unstructured":"G. E. Moore . Cramming more components onto integrated circuits. phElectronics, 38 (8) , April 1965 . G. E. Moore. Cramming more components onto integrated circuits. phElectronics, 38 (8), April 1965."},{"key":"e_1_3_2_2_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/368434.368755"},{"key":"e_1_3_2_2_25_1","unstructured":"SPEC. Standard performance evaluation corporation 2011. URL http:\/\/www.spec.org.  SPEC. Standard performance evaluation corporation 2011. URL http:\/\/www.spec.org."},{"key":"e_1_3_2_2_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508274"},{"key":"e_1_3_2_2_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"e_1_3_2_2_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.494"}],"event":{"name":"ISCA '11: The 38th Annual International Symposium on Computer Architecture","location":"San Jose California USA","acronym":"ISCA '11","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS"]},"container-title":["Proceedings of the 38th annual international symposium on Computer architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2000064.2000108","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2000064.2000108","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:54:09Z","timestamp":1750226049000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2000064.2000108"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6,4]]},"references-count":27,"alternative-id":["10.1145\/2000064.2000108","10.1145\/2000064"],"URL":"https:\/\/doi.org\/10.1145\/2000064.2000108","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2024723.2000108","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2011,6,4]]},"assertion":[{"value":"2011-06-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}