{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,8]],"date-time":"2026-05-08T14:23:07Z","timestamp":1778250187952,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,6,4]],"date-time":"2011-06-04T00:00:00Z","timestamp":1307145600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,6,4]]},"DOI":"10.1145\/2000064.2000112","type":"proceedings-article","created":{"date-parts":[[2011,6,28]],"date-time":"2011-06-28T13:34:50Z","timestamp":1309268090000},"page":"401-412","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":36,"title":["Kilo-NOC"],"prefix":"10.1145","author":[{"given":"Boris","family":"Grot","sequence":"first","affiliation":[{"name":"The University of Texas at Austin, Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joel","family":"Hestness","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin, Austin, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephen W.","family":"Keckler","sequence":"additional","affiliation":[{"name":"NVIDIA & The University of Texas at Austin, Santa Clara, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,6,4]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325115"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_2_6_1","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally W. J.","year":"2004","unstructured":"W. J. Dally and B. Towles . Principles and Practices of Interconnection Networks . Morgan Kaufmann Publishers Inc ., San Francisco, CA, USA, 2004 . W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2004."},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/75246.75248"},{"key":"e_1_3_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.90"},{"key":"e_1_3_2_2_9_1","first-page":"163","volume-title":"Express Cube Topologies for on-Chip Interconnects. In International Symposium on High-Performance Computer Architecture","author":"Grot B.","year":"2009","unstructured":"B. Grot , J. Hestness , S. W. Keckler , and O. Mutlu . Express Cube Topologies for on-Chip Interconnects. In International Symposium on High-Performance Computer Architecture , pages 163 -- 174 , February 2009 . B. Grot, J. Hestness, S. W. Keckler, and O. Mutlu. Express Cube Topologies for on-Chip Interconnects. In International Symposium on High-Performance Computer Architecture, pages 163--174, February 2009."},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669149"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1921249.1921258"},{"key":"e_1_3_2_2_12_1","volume-title":"http:\/\/www.itrs.net\/links\/2009ITRS\/Home2009.htm","year":"2009","unstructured":"International Technology Roadmap for Semiconductors. http:\/\/www.itrs.net\/links\/2009ITRS\/Home2009.htm , 2009 . International Technology Roadmap for Semiconductors. http:\/\/www.itrs.net\/links\/2009ITRS\/Home2009.htm, 2009."},{"key":"e_1_3_2_2_13_1","first-page":"423","volume-title":"Design, Automation, and Test in Europe","author":"Kahng A.","year":"2009","unstructured":"A. Kahng , B. Li , L.-S. Peh , and K. Samadi . ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-stage Design Space Exploration . In Design, Automation, and Test in Europe , pages 423 -- 428 , April 2009 . A. Kahng, B. Li, L.-S. Peh, and K. Samadi. ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-stage Design Space Exploration. In Design, Automation, and Test in Europe, pages 423--428, April 2009."},{"key":"e_1_3_2_2_14_1","first-page":"267","article-title":"Virtual Cut-through: a New Computer Communication Switching Technique","volume":"3","author":"Kermani P.","year":"1979","unstructured":"P. Kermani and L. Kleinrock . Virtual Cut-through: a New Computer Communication Switching Technique . Computer Networks , 3 : 267 -- 286 , September 1979 . P. Kermani and L. Kleinrock. Virtual Cut-through: a New Computer Communication Switching Technique. Computer Networks, 3:267--286, September 1979.","journal-title":"Computer Networks"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669145"},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.15"},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.14"},{"key":"e_1_3_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250681"},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.31"},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250670"},{"key":"e_1_3_2_2_21_1","first-page":"151","volume-title":"Elastic-buffer Flow Control for On-chip Networks. In International Symposium on High-Performance Computer Architecture","author":"Michelogiannakis G.","year":"2009","unstructured":"G. Michelogiannakis , J. Balfour , and W. Dally . Elastic-buffer Flow Control for On-chip Networks. In International Symposium on High-Performance Computer Architecture , pages 151 -- 162 , February 2009 . G. Michelogiannakis, J. Balfour, and W. Dally. Elastic-buffer Flow Control for On-chip Networks. In International Symposium on High-Performance Computer Architecture, pages 151--162, February 2009."},{"key":"e_1_3_2_2_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555781"},{"key":"e_1_3_2_2_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"e_1_3_2_2_24_1","unstructured":"NVIDIA. NVIDIA's Next Generation CUDA Compute Architecture: Fermi. http:\/\/www.nvidia.com\/content\/ PDF\/fermi_white_papers\/NVIDIA_ Fermi_Compute_Architecture_Whitepaper.pdf 2009.  NVIDIA. NVIDIA's Next Generation CUDA Compute Architecture: Fermi. http:\/\/www.nvidia.com\/content\/ PDF\/fermi_white_papers\/NVIDIA_ Fermi_Compute_Architecture_Whitepaper.pdf 2009."},{"key":"e_1_3_2_2_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859896"},{"key":"e_1_3_2_2_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001949"},{"key":"e_1_3_2_2_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434030"},{"key":"e_1_3_2_2_28_1","unstructured":"Tilera TILE-Gx100. http:\/\/www.tilera.com\/products\/TILE-Gx.php.  Tilera TILE-Gx100. http:\/\/www.tilera.com\/products\/TILE-Gx.php."},{"key":"e_1_3_2_2_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612254"},{"key":"e_1_3_2_2_30_1","first-page":"105","volume-title":"Power-driven Design of Router Microarchitectures in On-chip Networks. In International Symposium on Microarchitecture","author":"Wang H.","year":"2003","unstructured":"H. Wang , L.-S. Peh , and S. Malik . Power-driven Design of Router Microarchitectures in On-chip Networks. In International Symposium on Microarchitecture , pages 105 -- 116 , December 2003 . H. Wang, L.-S. Peh, and S. Malik. Power-driven Design of Router Microarchitectures in On-chip Networks. In International Symposium on Microarchitecture, pages 105--116, December 2003."},{"key":"e_1_3_2_2_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.89"}],"event":{"name":"ISCA '11: The 38th Annual International Symposium on Computer Architecture","location":"San Jose California USA","acronym":"ISCA '11","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS"]},"container-title":["Proceedings of the 38th annual international symposium on Computer architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2000064.2000112","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2000064.2000112","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:54:09Z","timestamp":1750226049000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2000064.2000112"}},"subtitle":["a heterogeneous network-on-chip architecture for scalability and service guarantees"],"short-title":[],"issued":{"date-parts":[[2011,6,4]]},"references-count":31,"alternative-id":["10.1145\/2000064.2000112","10.1145\/2000064"],"URL":"https:\/\/doi.org\/10.1145\/2000064.2000112","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2024723.2000112","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2011,6,4]]},"assertion":[{"value":"2011-06-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}