{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,20]],"date-time":"2026-03-20T15:40:11Z","timestamp":1774021211116,"version":"3.50.1"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2011,8,1]],"date-time":"2011-08-01T00:00:00Z","timestamp":1312156800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"European ITEA2 project GEODES","award":["7013"],"award-info":[{"award-number":["7013"]}]},{"DOI":"10.13039\/501100004956","name":"Bundesministerium f\u00fcr Verkehr, Innovation und Technologie","doi-asserted-by":"publisher","award":["815069\/13511"],"award-info":[{"award-number":["815069\/13511"]}],"id":[{"id":"10.13039\/501100004956","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2011,8]]},"abstract":"<jats:p>Finite State Machines (FSMs) are a key element of integrated circuits. Hard-coded FSMs do not allow changes after the ASIC production. While an embedded FPGA IP core provides flexibility, it is a complex circuit, requires difficult synthesis tools, and is expensive. This article presents and evaluates a novel architecture that is specifically optimized for implementing reconfigurable finite state machines: Transition-based Reconfigurable FSM (TR-FSM). The architecture shows a considerable reduction in area, delay, and power consumption compared to FPGA architectures with a (nearly) FPGA-like reconfigurability.<\/jats:p>","DOI":"10.1145\/2000832.2000835","type":"journal-article","created":{"date-parts":[[2011,8,30]],"date-time":"2011-08-30T13:30:18Z","timestamp":1314711018000},"page":"1-14","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["TR-FSM"],"prefix":"10.1145","volume":"4","author":[{"given":"Johann","family":"Glaser","sequence":"first","affiliation":[{"name":"Vienna University of Technology, Austria"}]},{"given":"Markus","family":"Damm","sequence":"additional","affiliation":[{"name":"Vienna University of Technology, Austria"}]},{"given":"Jan","family":"Haase","sequence":"additional","affiliation":[{"name":"Vienna University of Technology, Austria"}]},{"given":"Christoph","family":"Grimm","sequence":"additional","affiliation":[{"name":"Vienna University of Technology, Austria"}]}],"member":"320","published-online":{"date-parts":[[2011,8,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2002.803246"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). 3255--3258","author":"Alioto M.","unstructured":"Alioto , M. and Palumbo , G . 2007a. Design of fast large fan-in CMOS multiplexers accounting for interconnects . In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). 3255--3258 . Alioto, M. and Palumbo, G. 2007a. Design of fast large fan-in CMOS multiplexers accounting for interconnects. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). 3255--3258."},{"key":"e_1_2_1_3_1","first-page":"6","article-title":"Interconnect-Aware design of fast large fan-in CMOS multiplexers","volume":"54","author":"Alioto M.","year":"2007","unstructured":"Alioto , M. and Palumbo , G. 2007 b. Interconnect-Aware design of fast large fan-in CMOS multiplexers . IEEE Trans. Circ. Systems II: Express Briefs 54 , 6 . Alioto, M. and Palumbo, G. 2007b. Interconnect-Aware design of fast large fan-in CMOS multiplexers. IEEE Trans. Circ. Systems II: Express Briefs 54, 6.","journal-title":"IEEE Trans. Circ. Systems II: Express Briefs"},{"key":"e_1_2_1_5_1","unstructured":"Davis S. Reynolds C. and Zuchowski P. 2002. IBM licenses embedded FPGA cores from xilinx for use in SoC ASICs. Tech. rep. Xilinx Inc.  Davis S. Reynolds C. and Zuchowski P. 2002. IBM licenses embedded FPGA cores from xilinx for use in SoC ASICs. Tech. rep. Xilinx Inc."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-12133-3_13"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the Austrochip Conference.","author":"Glaser J.","unstructured":"Glaser , J. , Haase , J. , Damm , M. , and Grimm , C . 2009. Investigating power-reduction for a reconfigurable sensor interface . In Proceedings of the Austrochip Conference. Glaser, J., Haase, J., Damm, M., and Grimm, C. 2009. Investigating power-reduction for a reconfigurable sensor interface. In Proceedings of the Austrochip Conference."},{"key":"e_1_2_1_8_1","unstructured":"Glaser J. Haase J. Damm M. and Grimm C. 2010b. A novel reconfigurable architecture for wireless sensor networks. In Tagungsband zur Informationstagung Mikroelektronik 10. OVE 284--288.  Glaser J. Haase J. Damm M. and Grimm C. 2010b. A novel reconfigurable architecture for wireless sensor networks. In Tagungsband zur Informationstagung Mikroelektronik 10. OVE 284--288."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the 7th IEEE, IET International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP). 343--347","author":"Glaser J.","unstructured":"Glaser , J. , Haase , J. , and Grimm , C . 2010c. Designing a reconfigurable architecture for ultra-low power wireless sensors . In Proceedings of the 7th IEEE, IET International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP). 343--347 . Glaser, J., Haase, J., and Grimm, C. 2010c. Designing a reconfigurable architecture for ultra-low power wireless sensors. In Proceedings of the 7th IEEE, IET International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP). 343--347."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370535"},{"key":"e_1_2_1_11_1","volume-title":"Contemporary Logic Design. The Benjamin\/Cummings Publishing Company","author":"Katz R. H.","unstructured":"Katz , R. H. 1994. Contemporary Logic Design. The Benjamin\/Cummings Publishing Company , Inc . Katz, R. H. 1994. Contemporary Logic Design. The Benjamin\/Cummings Publishing Company, Inc."},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the International Symposium on Circuits and Systems (ISCAS). 4374--4377","author":"Liu Z.","unstructured":"Liu , Z. , Arslan , T. , and Erdogan , A. T . 2006. An embedded low power reconfigurable fabric for finite state machine operations . In Proceedings of the International Symposium on Circuits and Systems (ISCAS). 4374--4377 . Liu, Z., Arslan, T., and Erdogan, A. T. 2006. An embedded low power reconfigurable fabric for finite state machine operations. In Proceedings of the International Symposium on Circuits and Systems (ISCAS). 4374--4377."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120983"},{"key":"e_1_2_1_14_1","unstructured":"McElvain K. 1993. LGSynth93 benchmark set: Version 4.0. http:\/\/www.cbl.ncsu.edu\/pub\/Benchmark_dirs\/LGSynth93\/.  McElvain K. 1993. LGSynth93 benchmark set: Version 4.0. http:\/\/www.cbl.ncsu.edu\/pub\/Benchmark_dirs\/LGSynth93\/."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2007.64"},{"key":"e_1_2_1_16_1","unstructured":"Rabaey J. M. Chandrakasan A. and Nikolic B. 2003. Digital Integrated Circuits. Prentice Hall Upper Saddle River NJ.   Rabaey J. M. Chandrakasan A. and Nikolic B. 2003. Digital Integrated Circuits. Prentice Hall Upper Saddle River NJ."},{"key":"e_1_2_1_17_1","unstructured":"SiliconBlue Technologies Corporation. 2010a. DiePlus Advantage. SiliconBlue Technologies Corporation.  SiliconBlue Technologies Corporation. 2010a. DiePlus Advantage. SiliconBlue Technologies Corporation."},{"key":"e_1_2_1_18_1","volume-title":"iCE65 Ultra Low-Power mobileFPGA Family","author":"SiliconBlue Technologies Corporation","unstructured":"SiliconBlue Technologies Corporation . 2010b. iCE65 Ultra Low-Power mobileFPGA Family . SiliconBlue Technologies Corporation . SiliconBlue Technologies Corporation. 2010b. iCE65 Ultra Low-Power mobileFPGA Family. SiliconBlue Technologies Corporation."}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2000832.2000835","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2000832.2000835","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:00:03Z","timestamp":1750244403000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2000832.2000835"}},"subtitle":["Transition-Based reconfigurable finite state machine"],"short-title":[],"issued":{"date-parts":[[2011,8]]},"references-count":17,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2011,8]]}},"alternative-id":["10.1145\/2000832.2000835"],"URL":"https:\/\/doi.org\/10.1145\/2000832.2000835","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,8]]},"assertion":[{"value":"2010-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-08-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}