{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T05:54:51Z","timestamp":1775454891020,"version":"3.50.1"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2011,8,1]],"date-time":"2011-08-01T00:00:00Z","timestamp":1312156800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2011,8]]},"abstract":"<jats:p>This work presents a new automatic mechanism to explore the solution space between Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This new solution is termed as an Application-Specific Inflexible FPGA (ASIF) [Parvez et al. 2009]. An ASIF can be considered as an FPGA with reduced flexibility, or as a reconfigurable ASIC that can implement a set of application circuits which will operate at mutually exclusive times. Execution of different application circuits can be switched by loading their respective bitstream on an ASIF. An ASIF that is reduced from a heterogeneous FPGA is termed as a heterogeneous ASIF. It is shown that a standard-cell-based heterogeneous ASIF for a set of 10 opencore application circuits is 9.6 times smaller than a single-driver mesh-based heterogeneous FPGA. The area gap between ASIC and ASIF is not too significant; however, it can be reduced by designing repeatedly used components of ASIF in full-custom. Unlike an ASIC, an ASIF is a reprogrammable device that can be used to reprogram new or modified circuits at a limited scale.<\/jats:p>","DOI":"10.1145\/2000832.2000836","type":"journal-article","created":{"date-parts":[[2011,8,30]],"date-time":"2011-08-30T13:30:18Z","timestamp":1314711018000},"page":"1-14","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Application-Specific FPGA using heterogeneous logic blocks"],"prefix":"10.1145","volume":"4","author":[{"given":"Husain","family":"Parvez","sequence":"first","affiliation":[{"name":"Universit\u00e9 Pierre et Marie Curie, Paris, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zied","family":"Marrakchi","sequence":"additional","affiliation":[{"name":"Flexras Technologies, Paris, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alp","family":"Kilic","sequence":"additional","affiliation":[{"name":"Universit\u00e9 Pierre et Marie Curie, Paris, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[{"name":"Universit\u00e9 Pierre et Marie Curie, Paris, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,8,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Betz V. Marquardt A. and Rose J. 1999. In Architecture and CAD for Deep-Submicron FPGAs.   Betz V. Marquardt A. and Rose J. 1999. In Architecture and CAD for Deep-Submicron FPGAs.","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"e_1_2_1_3_1","volume-title":"Berkeley Logic Synthesis and Verification Group","unstructured":"BLIF. 2011. Berkeley Logic Synthesis and Verification Group , University of California , Berkeley. http:\/\/vlsi.colorado.edu\/~vis\/blif.ps. BLIF. 2011. Berkeley Logic Synthesis and Verification Group, University of California, Berkeley. http:\/\/vlsi.colorado.edu\/~vis\/blif.ps."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1035"},{"key":"e_1_2_1_5_1","unstructured":"eASIC. 2011. www.easic.com.  eASIC. 2011. www.easic.com."},{"key":"e_1_2_1_6_1","unstructured":"HardCopy. IV. 2011. HardCopy IV ASICs Device Handbook. http:\/\/www.altera.com\/products\/devices\/hardcopy-asics\/hardcopy-iv\/literature\/hciv-literature.jsp.  HardCopy. IV. 2011. HardCopy IV ASICs Device Handbook. http:\/\/www.altera.com\/products\/devices\/hardcopy-asics\/hardcopy-iv\/literature\/hciv-literature.jsp."},{"key":"e_1_2_1_7_1","first-page":"64","article-title":"A methodology for FPGA to structured-ASIC synthesis and verification","volume":"2","author":"Hutton M.","year":"2006","unstructured":"Hutton , M. , Yuan , R. , Schleicher , J. , Baeckler , G. , Cheung , S. , Chua , K. , and Phoon , H. 2006 . A methodology for FPGA to structured-ASIC synthesis and verification . In Proceedings of DATE 2 , 64 -- 69 . Hutton, M., Yuan, R., Schleicher, J., Baeckler, G., Cheung, S., Chua, K., and Phoon, H. 2006. A methodology for FPGA to structured-ASIC synthesis and verification. In Proceedings of DATE 2, 64--69.","journal-title":"Proceedings of DATE"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Kirkpatrick Gelatt and Hecchi. 1983. Optimisation by simulated annealing. Sci. 220 4598 671--680.  Kirkpatrick Gelatt and Hecchi. 1983. Optimisation by simulated annealing. Sci. 220 4598 671--680.","DOI":"10.1126\/science.220.4598.671"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1287\/opre.14.4.699"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the International Conference on Field Programmable Technology (ICFPT).","author":"Lemieux G.","unstructured":"Lemieux , G. , Lee , E. , Tom , M. , and Yu , A . 2004. Directional and single-driver wires in FPGA interconnect . In Proceedings of the International Conference on Field Programmable Technology (ICFPT). Lemieux, G., Lee, E., Tom, M., and Yu, A. 2004. Directional and single-driver wires in FPGA interconnect. In Proceedings of the International Conference on Field Programmable Technology (ICFPT)."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"e_1_2_1_13_1","volume-title":"Proceedings of the International Conference on Field Programmable Technology (ICFPT'09)","author":"Parvez H.","unstructured":"Parvez , H. , Marrakchi , Z. , and Mehrez , H . 2009. ASIF: Application specific inflexible FPGA . In Proceedings of the International Conference on Field Programmable Technology (ICFPT'09) . Parvez, H., Marrakchi, Z., and Mehrez, H. 2009. ASIF: Application specific inflexible FPGA. In Proceedings of the International Conference on Field Programmable Technology (ICFPT'09)."},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'07)","author":"Pistorius J.","unstructured":"Pistorius , J. , Hutton , M. , Schleicher , J. , Iotov , M. , Julias , E. , and Tharmalignam , K . 2007. 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