{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:26:02Z","timestamp":1750307162810,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2011,10,1]],"date-time":"2011-10-01T00:00:00Z","timestamp":1317427200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2011,10]]},"abstract":"<jats:p>In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (field programmable gate arrays) can be configured with a specialized circuit each time the parameter values change. This technique is called dynamic data folding. The specialized circuits are smaller and faster than their generic counterparts. However, the overhead involved in generating the configurations for the specialized circuits at runtime is very large when conventional tools are used, and this overhead will in many cases negate the benefit of using optimized configurations.<\/jats:p>\n          <jats:p>This article introduces an automatic method for generating runtime parameterizable configurations from arbitrary Boolean circuits. These configurations, in which some of the configuration bits are expressed as a closed-form Boolean expression of a set of parameters, enable very fast run-time specialization, since specialization only involves evaluating these expressions. Our approach is validated on a ternary content-addressable memory (TCAM). We show that the specialized configurations, produced by our method use 2.82 times fewer LUTs than the generic configuration, and even 1.41 times fewer LUTs than the implementation generated by Xilinx Coregen. Moreover, while Coregen needs hand-crafted generators for each type of circuit, our toolflow can be applied to any VHDL design. Using our automatic and generally applicable method, run-time hardware optimization suddenly becomes feasible for a large class of applications.<\/jats:p>","DOI":"10.1145\/2003695.2003703","type":"journal-article","created":{"date-parts":[[2011,10,25]],"date-time":"2011-10-25T12:23:05Z","timestamp":1319545385000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":27,"title":["Dynamic data folding with parameterizable FPGA configurations"],"prefix":"10.1145","volume":"16","author":[{"given":"Karel","family":"Bruneel","sequence":"first","affiliation":[{"name":"Ghent University, Ghent, Belgium"}]},{"given":"Wim","family":"Heirman","sequence":"additional","affiliation":[{"name":"Ghent University, Ghent, Belgium"}]},{"given":"Dirk","family":"Stroobandt","sequence":"additional","affiliation":[{"name":"Ghent University, Ghent, Belgium"}]}],"member":"320","published-online":{"date-parts":[[2011,10,27]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera. 2001. Application note 119: Implementing high-speed search applications with Altera CAM Altera.  Altera. 2001. Application note 119: Implementing high-speed search applications with Altera CAM Altera."},{"volume-title":"ABC: A system for sequential synthesis and verification","author":"Berkeley Logic Synthesis and Verification Group","key":"e_1_2_1_2_1","unstructured":"Berkeley Logic Synthesis and Verification Group . ABC: A system for sequential synthesis and verification . Berkeley Logic Synthesis and Verification Group . Berkeley Logic Synthesis and Verification Group. ABC: A system for sequential synthesis and verification. Berkeley Logic Synthesis and Verification Group."},{"volume-title":"Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications (FPL'97)","author":"Betz V.","key":"e_1_2_1_3_1","unstructured":"Betz , V. and Rose , J . 1997. VPR: A new packing, placement and routing tool for FPGA research . In Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications (FPL'97) . Springer, Berlin, 213--222. Betz, V. and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications (FPL'97). Springer, Berlin, 213--222."},{"volume-title":"The AIGER and-Inverter Graph (AIG) format","author":"Biere A.","key":"e_1_2_1_4_1","unstructured":"Biere , A. 2007. The AIGER and-Inverter Graph (AIG) format . Johannes Kepler University . Biere, A. 2007. The AIGER and-Inverter Graph (AIG) format. Johannes Kepler University."},{"key":"e_1_2_1_5_1","unstructured":"Brelet J.-L. and New B. 1999. XAPP203: Designing flexible fast CAMs with Virtex family FPGAs. Xilinx.  Brelet J.-L. and New B. 1999. XAPP203: Designing flexible fast CAMs with Virtex family FPGAs. Xilinx."},{"volume-title":"Proceedings of the Design, Automation and Test in Europe. 964--969","author":"Bruneel K.","key":"e_1_2_1_6_1","unstructured":"Bruneel , K. , Abouelella , F. , and Stroobandt , D . 2009. Automatically mapping applications to a self-reconfiguring platform . In Proceedings of the Design, Automation and Test in Europe. 964--969 . Bruneel, K., Abouelella, F., and Stroobandt, D. 2009. Automatically mapping applications to a self-reconfiguring platform. In Proceedings of the Design, Automation and Test in Europe. 964--969."},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications. 35--40","author":"Bruneel K.","key":"e_1_2_1_7_1","unstructured":"Bruneel , K. , Bertels , P. , and Stroobandt , D . 2007. A method for fast hardware specialization at run-time . In Proceedings of the International Conference on Field Programmable Logic and Applications. 35--40 . Bruneel, K., Bertels, P., and Stroobandt, D. 2007. A method for fast hardware specialization at run-time. In Proceedings of the International Conference on Field Programmable Logic and Applications. 35--40."},{"volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications. 361--366","author":"Bruneel K.","key":"e_1_2_1_8_1","unstructured":"Bruneel , K. and Stroobandt , D . 2008a. Automatic generation of run-time parameterizable configurations . In Proceedings of the International Conference on Field Programmable Logic and Applications. 361--366 . Bruneel, K. and Stroobandt, D. 2008a. Automatic generation of run-time parameterizable configurations. In Proceedings of the International Conference on Field Programmable Logic and Applications. 361--366."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2008.26"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-12133-3_20"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240669"},{"key":"e_1_2_1_12_1","first-page":"10","article-title":"Fast integer multipliers fit in FPGAs","volume":"39","author":"Chapman K.","year":"1993","unstructured":"Chapman , K. 1993 . Fast integer multipliers fit in FPGAs . EDN 39 , 10 , 80. Chapman, K. 1993. Fast integer multipliers fit in FPGAs. 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Assisting network intrusion detection with reconfigurable hardware . In Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE , Los, Alamitos, CA, 111--120. Hutchings, B., Franklin, R., and Carver, D. 2002. Assisting network intrusion detection with reconfigurable hardware. In Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE, Los, Alamitos, CA, 111--120."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804386"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/90.731185"},{"volume-title":"Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE","author":"Lemoine E.","key":"e_1_2_1_20_1","unstructured":"Lemoine , E. and Merceron , D . 1995. Run-time reconfiguration of FPGA for scanning genomic databases . In Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE , Los Alamitos, CA. Lemoine, E. and Merceron, D. 1995. Run-time reconfiguration of FPGA for scanning genomic databases. In Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE, Los Alamitos, CA."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1142980.1142986"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882119"},{"volume-title":"InProceedings of the 9th International Workshop on Field-Programmable Logic and Applications (FPL'99)","author":"McGregor G.","key":"e_1_2_1_23_1","unstructured":"McGregor , G. and Lysaght , P . 1999. Self-controlling dynamic reconfiguration: A case study . InProceedings of the 9th International Workshop on Field-Programmable Logic and Applications (FPL'99) . Springer, Berlin, 144--154. McGregor, G. and Lysaght, P. 1999. Self-controlling dynamic reconfiguration: A case study. InProceedings of the 9th International Workshop on Field-Programmable Logic and Applications (FPL'99). Springer, Berlin, 144--154."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"volume-title":"InProceedings of the 16th International Conference on VLSI Design. 561--566","author":"Puttegowda K.","key":"e_1_2_1_26_1","unstructured":"Puttegowda , K. , Worek , W. , Pappas , N. , Dandapani , A. , Athanas , P. , and Dickerman , A . 2003. A run-time reconfigurable system for gene-sequence searching . InProceedings of the 16th International Conference on VLSI Design. 561--566 . Puttegowda, K., Worek, W., Pappas, N., Dandapani, A., Athanas, P., and Dickerman, A. 2003. A run-time reconfigurable system for gene-sequence searching. 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