{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:50:22Z","timestamp":1750308622577,"version":"3.41.0"},"reference-count":23,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2011,10,1]],"date-time":"2011-10-01T00:00:00Z","timestamp":1317427200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2011,10]]},"abstract":"<jats:p>Simultaneous multithreading processors dynamically share processor resources between multiple threads. In general, shared SMT resources may be managed explicitly, for instance, by dynamically setting queue occupation bounds for each thread as in the DCRA and Hill-Climbing policies. Alternatively, resources may be managed implicitly; that is, resource usage is controlled by placing the desired instruction mix in the resources. In this case, the main resource management tool is the instruction fetch policy which must predict the behavior of each thread (branch mispredictions, long-latency loads, etc.) as it fetches instructions.<\/jats:p>\n          <jats:p>In this article, we present the use of Speculative Instruction Window Weighting (SIWW) to bridge the gap between implicit and explicit SMT fetch policies. SIWW estimates for each thread the amount of outstanding work in the processor pipeline. Fetch proceeds for the thread with the least amount of work left. SIWW policies are implicit as fetch proceeds for the thread with the least amount of work left. They are also explicit as maximum resource allocation can also be set. SIWW can use and combine virtually any of the indicators that were previously proposed for guiding the instruction fetch policy (number of in-flight instructions, number of low confidence branches, number of predicted cache misses, etc.). Therefore, SIWW is an approach to designing SMT fetch policies, rather than a particular fetch policy.<\/jats:p>\n          <jats:p>Targeting fairness or throughput is often contradictory and a SMT scheduling policy often optimizes only one performance metric at the sacrifice of the other metric. Our simulations show that the SIWW fetch policy can achieve at the same time state-of-the-art throughput, state-of-the-art fairness and state-of-the-art harmonic performance mean.<\/jats:p>","DOI":"10.1145\/2019608.2019611","type":"journal-article","created":{"date-parts":[[2011,10,18]],"date-time":"2011-10-18T13:01:58Z","timestamp":1318942918000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Managing SMT resource usage through speculative instruction window weighting"],"prefix":"10.1145","volume":"8","author":[{"given":"Hans","family":"Vandierendonck","sequence":"first","affiliation":[{"name":"Ghent University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andr\u00e9","family":"Seznec","sequence":"additional","affiliation":[{"name":"IRISA\/INRIA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,10,18]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-39707-6_6"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.17"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.25"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006708"},{"volume-title":"Proceedings of the 11th International Conference on Parallel Architectures and Compilation Techniques. 30--41","author":"Dorai G. K.","key":"e_1_2_1_5_1","unstructured":"Dorai , G. K. and Yeung , D . 2002. Transparent threads: Resource sharing in SMT processors for high single-thread performance . In Proceedings of the 11th International Conference on Parallel Architectures and Compilation Techniques. 30--41 . Dorai, G. K. and Yeung, D. 2002. Transparent threads: Resource sharing in SMT processors for high single-thread performance. In Proceedings of the 11th International Conference on Parallel Architectures and Compilation Techniques. 30--41."},{"volume-title":"Proceedings of the 30th Symposium on Microarchitecture.","author":"Driesen K.","key":"e_1_2_1_6_1","unstructured":"Driesen , K. and Holzle , U . 1998. The cascaded predictor: Economical and adaptive branch target prediction . In Proceedings of the 30th Symposium on Microarchitecture. Driesen, K. and Holzle, U. 1998. The cascaded predictor: Economical and adaptive branch target prediction. In Proceedings of the 30th Symposium on Microarchitecture."},{"volume-title":"Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA'03)","author":"El-Moursy A.","key":"e_1_2_1_7_1","unstructured":"El-Moursy , A. and Albonesi , D. H . 2003. Front-end policies for improved issue efficiency in SMT processors . In Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA'03) . 31--40. El-Moursy, A. and Albonesi, D. H. 2003. Front-end policies for improved issue efficiency in SMT processors. In Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA'03). 31--40."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346201"},{"volume-title":"Proceedings of the 5th International Conference on Parallel Architectures and Compilation Techniques. 169--173","author":"Hily S.","key":"e_1_2_1_9_1","unstructured":"Hily , S. and Seznec , A . 1996. Branch prediction and simultaneous multithreading . In Proceedings of the 5th International Conference on Parallel Architectures and Compilation Techniques. 169--173 . Hily, S. and Seznec, A. 1996. Branch prediction and simultaneous multithreading. In Proceedings of the 5th International Conference on Parallel Architectures and Compilation Techniques. 169--173."},{"key":"e_1_2_1_10_1","unstructured":"Jimenez D. A. and Lin C. 2002. Composite confidence estimators for enhanced speculation control. Tech. rep. TR-0214 Dept. of Computer Sciences University of Texas at Austin.  Jimenez D. A. and Lin C. 2002. Composite confidence estimators for enhanced speculation control. Tech. rep. TR-0214 Dept. of Computer Sciences University of Texas at Austin."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.1289290"},{"volume-title":"Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDFS'04)","author":"Kang D.","key":"e_1_2_1_12_1","unstructured":"Kang , D. and Gaudiot , J . -L. 2004. Speculation control for simultaneous multithreading . In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDFS'04) . 76--85. Kang, D. and Gaudiot, J.-L. 2004. Speculation control for simultaneous multithreading. In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDFS'04). 76--85."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/263326.263382"},{"volume-title":"Proceedings of the 15th International Parallel & Distributed Processing Symposium.","author":"Luo K.","key":"e_1_2_1_14_1","unstructured":"Luo , K. , Franklin , M. , Mukherjee , S. S. , and Seznec , A . 2001a. Boosting SMT perfonnance by speculation control . In Proceedings of the 15th International Parallel & Distributed Processing Symposium. Luo, K., Franklin, M., Mukherjee, S. S., and Seznec, A. 2001a. Boosting SMT perfonnance by speculation control. In Proceedings of the 15th International Parallel & Distributed Processing Symposium."},{"volume-title":"Proceedings of the IEEE International Symposium on Perfonnance Analysis of Systems and Software (ISPASS). 164--171","author":"Luo K.","key":"e_1_2_1_15_1","unstructured":"Luo , K. , Gummaraju , J. , and Franklin , M . 2001b. Balancing throughput and fairness in SMT processors . In Proceedings of the IEEE International Symposium on Perfonnance Analysis of Systems and Software (ISPASS). 164--171 . Luo, K., Gummaraju, J., and Franklin, M. 2001b. Balancing throughput and fairness in SMT processors. In Proceedings of the IEEE International Symposium on Perfonnance Analysis of Systems and Software (ISPASS). 164--171."},{"volume-title":"Proceedings of the 17th International Conference on Machine Learning. 727--734","author":"Pelleo D.","key":"e_1_2_1_16_1","unstructured":"Pelleo , D. and Moore , A . 2000. X-means: Extending k-means with efficient estimation of the number of clusters . In Proceedings of the 17th International Conference on Machine Learning. 727--734 . Pelleo, D. and Moore, A. 2000. X-means: Extending k-means with efficient estimation of the number of clusters. In Proceedings of the 17th International Conference on Machine Learning. 727--734."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2005.2"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.13"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"volume-title":"Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture. IEEE Computer Society, 318--327","author":"Tullsen D. M.","key":"e_1_2_1_20_1","unstructured":"Tullsen , D. M. and Brown , J. A . 2001. Handling long-latency loads in a simultaneous multithreading processor . In Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture. IEEE Computer Society, 318--327 . Tullsen, D. M. and Brown, J. A. 2001. Handling long-latency loads in a simultaneous multithreading processor. In Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture. IEEE Computer Society, 318--327."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232993"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224449"},{"volume-title":"Proceedings of the 2nd HiPEAC Conference. 120--135","author":"Vandierendonck H.","key":"e_1_2_1_23_1","unstructured":"Vandierendonck , H. and Seznec , A . 2007. Fetch gating control through speculative instruction window weighting . In Proceedings of the 2nd HiPEAC Conference. 120--135 . Vandierendonck, H. and Seznec, A. 2007. Fetch gating control through speculative instruction window weighting. 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