{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:28:45Z","timestamp":1750307325208,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,6,5]],"date-time":"2011-06-05T00:00:00Z","timestamp":1307232000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0916636","CCF-0746850"],"award-info":[{"award-number":["CCF-0916636","CCF-0746850"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,6,5]]},"DOI":"10.1145\/2024724.2024921","type":"proceedings-article","created":{"date-parts":[[2011,9,6]],"date-time":"2011-09-06T15:10:46Z","timestamp":1315321846000},"page":"884-889","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Universal logic modules based on double-gate carbon nanotube transistors"],"prefix":"10.1145","author":[{"given":"Andrew","family":"Zukoski","sequence":"first","affiliation":[{"name":"Rice University, Houston"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuebei","family":"Yang","sequence":"additional","affiliation":[{"name":"Rice University, Houston"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kartik","family":"Mohanram","sequence":"additional","affiliation":[{"name":"Rice University, Houston"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,6,5]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2007.300"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.89.106801"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature01797"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl049745j"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.907835"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278551"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391556"},{"key":"e_1_3_2_1_8_1","first-page":"622","volume-title":"Design Automation and Test in Europe","author":"M. H.","year":"2009","unstructured":"M. H. B. Jamaa et al., \"Logic circuits with ambipolar CNTFETs: Novel opportunities for multi-level logic synthesis,\" in Proc . Design Automation and Test in Europe , pp. 622 -- 627 , 2009 . M. H. B. Jamaa et al., \"Logic circuits with ambipolar CNTFETs: Novel opportunities for multi-level logic synthesis,\" in Proc. Design Automation and Test in Europe, pp. 622--627, 2009."},{"key":"e_1_3_2_1_9_1","first-page":"65","volume-title":"Intl. Symposium on Nanoscale Architectures","author":"Marchi D.","year":"2010","unstructured":"D. Marchi fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications,\" in Proc . Intl. Symposium on Nanoscale Architectures , pp. 65 -- 70 , 2010 . D. Marchi et al., \"Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications,\" in Proc. Intl. Symposium on Nanoscale Architectures, pp. 65--70, 2010."},{"key":"e_1_3_2_1_10_1","first-page":"47","volume-title":"Intl. Symposium on Nanoscale Architectures","author":"Jabeur K.","year":"2010","unstructured":"K. Jabeur transistor count in clocked standard cells with am-bipolar double-gate FETs,\" in Proc . Intl. Symposium on Nanoscale Architectures , pp. 47 -- 52 , 2010 . K. Jabeur et al., \"Reducing transistor count in clocked standard cells with am-bipolar double-gate FETs,\" in Proc. Intl. Symposium on Nanoscale Architectures, pp. 47--52, 2010."},{"key":"e_1_3_2_1_11_1","volume-title":"NanoTCAD ViDES","author":"Fiori G.","year":"2008","unstructured":"G. Fiori and G. Iannaccone , \" NanoTCAD ViDES ,\" 2008 . DOI: 10254\/nanohubr5116.3. 10254\/nanohubr5116.3 G. Fiori and G. Iannaccone, \"NanoTCAD ViDES,\" 2008. DOI: 10254\/nanohubr5116.3."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.245595"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.821883"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.851427"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.909030"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283783"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.890384"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2010.2095826"},{"key":"e_1_3_2_1_19_1","volume-title":"Operation and modeling of the MOS transistors","author":"Tsividis Y.","year":"1999","unstructured":"Y. Tsividis , Operation and modeling of the MOS transistors . WCB\/McGraw-Hill , 1999 . Y. Tsividis, Operation and modeling of the MOS transistors. WCB\/McGraw-Hill, 1999."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.2006903"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.1993.289569"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240564"},{"key":"e_1_3_2_1_23_1","first-page":"1","volume-title":"Automation and Test in Europe","author":"Bernasconi A.","year":"2006","unstructured":"A. Bernasconi minimization of fully testable 2-spp networks,\" in Proc. Design , Automation and Test in Europe , pp. 1 -- 6 , 2006 . A. Bernasconi et al., \"Efficient minimization of fully testable 2-spp networks,\" in Proc. Design, Automation and Test in Europe, pp. 1--6, 2006."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/SWAT.1966.32"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1970.222879"},{"key":"e_1_3_2_1_26_1","first-page":"49","article-title":"A special class of Universal logic gate (ULG) and their evaluation under the walsh transform","volume":"44","author":"Edwards C.","year":"1979","unstructured":"C. Edwards , \" A special class of Universal logic gate (ULG) and their evaluation under the walsh transform ,\" Computers and Digital Techniques , vol. 44 , pp. 49 -- 59 , 1979 . C. Edwards, \"A special class of Universal logic gate (ULG) and their evaluation under the walsh transform,\" Computers and Digital Techniques, vol. 44, pp. 49--59, 1979.","journal-title":"Computers and Digital Techniques"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-e.1981.0040"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2002.1046267"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/577200"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2010.220"},{"key":"e_1_3_2_1_31_1","unstructured":"\"ABC Logic synthesis tool.\" Please visit the URL http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/for further details.  \"ABC Logic synthesis tool.\" Please visit the URL http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/for further details."}],"event":{"name":"DAC '11: The 48th Annual Design Automation Conference 2011","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE Council on Electronic Design Automation (CEDA)"],"location":"San Diego California","acronym":"DAC '11"},"container-title":["Proceedings of the 48th Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2024724.2024921","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2024724.2024921","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:05:59Z","timestamp":1750244759000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2024724.2024921"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6,5]]},"references-count":31,"alternative-id":["10.1145\/2024724.2024921","10.1145\/2024724"],"URL":"https:\/\/doi.org\/10.1145\/2024724.2024921","relation":{},"subject":[],"published":{"date-parts":[[2011,6,5]]},"assertion":[{"value":"2011-06-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}