{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:28:44Z","timestamp":1750307324521,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,6,5]],"date-time":"2011-06-05T00:00:00Z","timestamp":1307232000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,6,5]]},"DOI":"10.1145\/2024724.2024947","type":"proceedings-article","created":{"date-parts":[[2011,9,6]],"date-time":"2011-09-06T15:10:46Z","timestamp":1315321846000},"page":"1014-1019","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":21,"title":["Power-gated MOS current mode logic (PG-MCML)"],"prefix":"10.1145","author":[{"given":"Alessandro","family":"Cevrero","sequence":"first","affiliation":[{"name":"School of Engineering - EPFL, Lausanne, Switzerland and School of Computer and Communication Sciences - EPFL, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francesco","family":"Regazzoni","sequence":"additional","affiliation":[{"name":"ALaRI - University of Lugano, Lugano, Switzerland and UCL Crypto Group, Universit\u00e9 catholique de Louvain, Louvain-la-Neuve, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Micheal","family":"Schwander","sequence":"additional","affiliation":[{"name":"School of Engineering - EPFL, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephane","family":"Badel","sequence":"additional","affiliation":[{"name":"School of Engineering - EPFL, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Ienne","sequence":"additional","affiliation":[{"name":"School of Computer and Communication Sciences - EPFL, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yusuf","family":"Leblebici","sequence":"additional","affiliation":[{"name":"School of Engineering - EPFL, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,6,5]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.910495"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403581"},{"key":"e_1_3_2_1_3_1","series-title":"Lecture Notes in Computer Science pages 16--29","volume-title":"M. Joye and J.-J","author":"Clavier E. Brier C.","year":"2004","unstructured":"E. Brier C. Clavier and F. Olivier . Correlation power analysis with a leakage model . In M. Joye and J.-J . Quisquater, editors, Cryptographic Hardware and Embedded Systems---CHES 2004 volume 3156 of Lecture Notes in Computer Science pages 16--29 . Springer , Berlin, Sept. 2004. E. Brier C. Clavier and F. Olivier. Correlation power analysis with a leakage model. In M. Joye and J.-J. Quisquater, editors, Cryptographic Hardware and Embedded Systems---CHES 2004 volume 3156 of Lecture Notes in Computer Science pages 16--29. Springer, Berlin, Sept. 2004."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1018437.1021791"},{"key":"e_1_3_2_1_5_1","volume-title":"ISCAS'04","volume":"4","author":"Bui H.","year":"2004","unstructured":"H. Bui and Y. Savaria . Shunt-peaking in MCML gates and its application in the design of a 20 Gb\/s half-rate phase detector. In Circuits and Systems 2004 . ISCAS'04 . Proceedings of the 2004 International Symposium on, volume 4 2004. H. Bui and Y. Savaria. Shunt-peaking in MCML gates and its application in the design of a 20 Gb\/s half-rate phase detector. In Circuits and Systems 2004. ISCAS'04. Proceedings of the 2004 International Symposium on, volume 4 2004."},{"key":"e_1_3_2_1_6_1","volume-title":"Power management of digital circuits in deep sub-micron CMOS technologies","author":"Henzler S.","year":"2006","unstructured":"S. Henzler . Power management of digital circuits in deep sub-micron CMOS technologies . Springer Verlag 2006 . S. Henzler. Power management of digital circuits in deep sub-micron CMOS technologies. Springer Verlag 2006."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329007"},{"key":"e_1_3_2_1_8_1","series-title":"Lecture Notes in Computer Science","first-page":"398","volume-title":"Advances in Cryptology---CRYPTO '99","author":"Kocher P.","year":"1999","unstructured":"P. Kocher , J. Jaffe , and B. Jun . Differential power analysis . In M. Wiener, editor, Advances in Cryptology---CRYPTO '99 , volume 1666 of Lecture Notes in Computer Science , pages 398 -- 412 . Springer , Berlin, Aug . 1999 . P. Kocher, J. Jaffe, and B. Jun. Differential power analysis. In M. Wiener, editor, Advances in Cryptology---CRYPTO '99, volume 1666 of Lecture Notes in Computer Science, pages 398--412. Springer, Berlin, Aug. 1999."},{"key":"e_1_3_2_1_9_1","volume-title":"Apr.","author":"Lampret D.","year":"2006","unstructured":"D. Lampret . OpenRISC 1000 Architecture Manual , Apr. 2006 . D. Lampret. OpenRISC 1000 Architecture Manual, Apr. 2006."},{"key":"e_1_3_2_1_10_1","volume-title":"Federal Information Processing Standards Publication","author":"Advanced Encryption NIST.","year":"2001","unstructured":"NIST. Announcing the Advanced Encryption Standard (AES). Federal Information Processing Standards Publication 197, November 2001 . NIST. Announcing the Advanced Encryption Standard (AES). Federal Information Processing Standards Publication 197, November 2001."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_13"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04138-9_15"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.924861"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_21"},{"key":"e_1_3_2_1_15_1","first-page":"403","volume-title":"Proceedings of the 28th European Solid-State Circuits Conference","author":"Tiri K.","year":"2002","unstructured":"K. Tiri , M. Akmal , and I. Verbauwhede . A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on Smart Cards . In Proceedings of the 28th European Solid-State Circuits Conference , pages 403 -- 406 , Florence , Sept. 2002 . K. Tiri, M. Akmal, and I. Verbauwhede. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on Smart Cards. In Proceedings of the 28th European Solid-State Circuits Conference, pages 403--6, Florence, Sept. 2002."},{"key":"e_1_3_2_1_16_1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"125","DOI":"10.1007\/978-3-540-45238-6_11","volume-title":"C. D. Walter, \u00c7etin Kaya Ko\u00e7, and C","author":"Tiri K.","year":"2003","unstructured":"K. Tiri and I. Verbauwhede . Securing encryption algorithms against DPA at the logic level: Next generation smart card technology . In C. D. Walter, \u00c7etin Kaya Ko\u00e7, and C . Paar, editors, Cryptographic Hardware and Embedded Systems---CHES 2003 , volume 2779 of Lecture Notes in Computer Science , pages 125 -- 136 . Springer , Berlin, Sept. 2003. K. Tiri and I. Verbauwhede. Securing encryption algorithms against DPA at the logic level: Next generation smart card technology. In C. D. Walter, \u00c7etin Kaya Ko\u00e7, and C. Paar, editors, Cryptographic Hardware and Embedded Systems---CHES 2003, volume 2779 of Lecture Notes in Computer Science, pages 125--136. Springer, Berlin, Sept. 2003."},{"issue":"10","key":"e_1_3_2_1_17_1","first-page":"1181","article-title":"An MOS current mode logic (MCML) circuit for low-power sub-GHz processors","volume":"75","author":"Yamashina M.","year":"1992","unstructured":"M. Yamashina and H. Yamada . An MOS current mode logic (MCML) circuit for low-power sub-GHz processors . IEICE Transactions on Electronics , 75 ( 10 ): 1181 -- 1187 , 1992 . M. Yamashina and H. Yamada. An MOS current mode logic (MCML) circuit for low-power sub-GHz processors. IEICE Transactions on Electronics, 75(10):1181--1187, 1992.","journal-title":"IEICE Transactions on Electronics"}],"event":{"name":"DAC '11: The 48th Annual Design Automation Conference 2011","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE Council on Electronic Design Automation (CEDA)"],"location":"San Diego California","acronym":"DAC '11"},"container-title":["Proceedings of the 48th Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2024724.2024947","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2024724.2024947","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:05:59Z","timestamp":1750244759000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2024724.2024947"}},"subtitle":["a power aware DPA-resistant standard cell library"],"short-title":[],"issued":{"date-parts":[[2011,6,5]]},"references-count":17,"alternative-id":["10.1145\/2024724.2024947","10.1145\/2024724"],"URL":"https:\/\/doi.org\/10.1145\/2024724.2024947","relation":{},"subject":[],"published":{"date-parts":[[2011,6,5]]},"assertion":[{"value":"2011-06-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}