{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T16:31:14Z","timestamp":1774801874705,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,10,9]],"date-time":"2011-10-09T00:00:00Z","timestamp":1318118400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,10,9]]},"DOI":"10.1145\/2038698.2038718","type":"proceedings-article","created":{"date-parts":[[2011,10,11]],"date-time":"2011-10-11T14:29:11Z","timestamp":1318343351000},"page":"115-124","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Architecting processors to allow voltage\/reliability tradeoffs"],"prefix":"10.1145","author":[{"given":"John","family":"Sartori","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rakesh","family":"Kumar","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,10,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629915"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_3_2_1_3_1","unstructured":"Cadence. Cadence LC User's Manual.  Cadence. Cadence LC User's Manual."},{"key":"e_1_3_2_1_4_1","unstructured":"Cadence. Cadence NC-Verilog User's Manual.  Cadence. Cadence NC-Verilog User's Manual."},{"key":"e_1_3_2_1_5_1","unstructured":"Cadence. Cadence SOCEncounter User's Manual.  Cadence. Cadence SOCEncounter User's Manual."},{"key":"e_1_3_2_1_6_1","first-page":"1110","volume-title":"DATE","author":"Chakrapani L.","year":"2006","unstructured":"L. Chakrapani , B. Akgul , S. Cheemalavagu , P. Korkmaz , K. Palem , and B. Seshasayee . Ultra-efficient (embedded) soc architectures based on probabilistic cmos (pcmos) technology . DATE , pages 1110 -- 1115 , 2006 . L. Chakrapani, B. Akgul, S. Cheemalavagu, P. Korkmaz, K. Palem, and B. Seshasayee. Ultra-efficient (embedded) soc architectures based on probabilistic cmos (pcmos) technology. DATE, pages 1110--1115, 2006."},{"key":"e_1_3_2_1_7_1","volume-title":"WARP","author":"Choudhary N.","year":"2009","unstructured":"N. Choudhary , S. Wadhavkar , T. Shah , S. Navada , H. Najaf-abadi, and E. Rotenberg . Fabscalar . In WARP , 2009 . N. Choudhary, S. Wadhavkar, T. Shah, S. Navada, H. Najaf-abadi, and E. Rotenberg. Fabscalar. In WARP, 2009."},{"key":"e_1_3_2_1_8_1","volume-title":"Intel atom processor z5xx series","author":"I. Corporation","year":"2008","unstructured":"I. Corporation . Intel atom processor z5xx series . 2008 . I. Corporation. Intel atom processor z5xx series. 2008."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566437"},{"key":"e_1_3_2_1_10_1","first-page":"7","author":"Ernst D.","year":"2003","unstructured":"D. Ernst , N. S. Kim , S. Das , S. Pant , R. Rao , T. Pham , C. Ziesler , D. Blaauw , T. Austin , K. Flautner , and T. Mudge . Razor: A low-power pipeline based on circuit-level timing speculation. In MICRO, page 7 , 2003 . D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge. Razor: A low-power pipeline based on circuit-level timing speculation. In MICRO, page 7, 2003.","journal-title":"In MICRO, page"},{"key":"e_1_3_2_1_11_1","volume-title":"ISSCC","author":"Fujimura Y.","year":"2010","unstructured":"Y. Fujimura , O. Hirabayashi , T. Sasaki , A. Suzuki , A. Kawasumi , Y. Takeyama , K. Kushida , G. Fukano , A. Katayama , Y. Niki , and T. Yabe . A configurable sram with constant-negative-level write buffer for low voltage operation with 0.149\u03bc m 2 cell in 32nm high-k\/metal gate cmos . In ISSCC , 2010 . Y. Fujimura, O. Hirabayashi, T. Sasaki, A. Suzuki, A. Kawasumi, Y. Takeyama, K. Kushida, G. Fukano, A. Katayama, Y. Niki, and T. Yabe. A configurable sram with constant-negative-level write buffer for low voltage operation with 0.149\u03bc m 2 cell in 32nm high-k\/metal gate cmos. In ISSCC, 2010."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299049"},{"key":"e_1_3_2_1_13_1","volume-title":"JILP","author":"Hamerly G.","year":"2005","unstructured":"G. Hamerly , E. Perelman , J. Lau , and B. Calder . Simpoint 3.0: Faster and more flexible program analysis . In JILP , 2005 . G. Hamerly, E. Perelman, J. Lau, and B. Calder. Simpoint 3.0: Faster and more flexible program analysis. In JILP, 2005."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416652"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837481"},{"key":"e_1_3_2_1_16_1","volume-title":"ASPDAC","author":"Kahng A.","year":"2010","unstructured":"A. Kahng , S. Kang , R. Kumar , and J. Sartori . Slack redistribution for graceful degradation under voltage overscaling . In ASPDAC , 2010 . A. Kahng, S. Kang, R. Kumar, and J. Sartori. Slack redistribution for graceful degradation under voltage overscaling. In ASPDAC, 2010."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1993.393383"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233587"},{"key":"e_1_3_2_1_19_1","volume-title":"DATE","author":"Narayanan S.","year":"2010","unstructured":"S. Narayanan , J. Sartori , R. Kumar , and D. Jones . Scalable stochastic processors . In DATE , 2010 . S. Narayanan, J. Sartori, R. Kumar, and D. Jones. Scalable stochastic processors. In DATE, 2010."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629929"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785533"},{"key":"e_1_3_2_1_23_1","unstructured":"Sun. Sun OpenSPARC Project.  Sun. Sun OpenSPARC Project."},{"key":"e_1_3_2_1_24_1","unstructured":"Synopsys. Synopsys Design Compiler User's Manual.  Synopsys. Synopsys Design Compiler User's Manual."},{"key":"e_1_3_2_1_25_1","unstructured":"Synopsys. Synopsys PrimeTime User's Manual.  Synopsys. Synopsys PrimeTime User's Manual."},{"key":"e_1_3_2_1_26_1","volume-title":"22nd Annual Computer Measurement Group Conference","author":"Tullsen D. M.","year":"1996","unstructured":"D. M. Tullsen . Simulation and modeling of a simultaneous multithreading processor . In 22nd Annual Computer Measurement Group Conference , 1996 . D. M. Tullsen. Simulation and modeling of a simultaneous multithreading processor. In 22nd Annual Computer Measurement Group Conference, 1996."},{"key":"e_1_3_2_1_27_1","unstructured":"University of Michigan. Bug Underground.  University of Michigan. Bug Underground."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647702"}],"event":{"name":"ESWeek '11: Seventh Embedded Systems Week","location":"Taipei Taiwan","acronym":"ESWeek '11","sponsor":["CEDA","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"]},"container-title":["Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2038698.2038718","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2038698.2038718","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:48:15Z","timestamp":1750240095000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2038698.2038718"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10,9]]},"references-count":28,"alternative-id":["10.1145\/2038698.2038718","10.1145\/2038698"],"URL":"https:\/\/doi.org\/10.1145\/2038698.2038718","relation":{},"subject":[],"published":{"date-parts":[[2011,10,9]]},"assertion":[{"value":"2011-10-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}