{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:14:01Z","timestamp":1763468041030,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,10,9]],"date-time":"2011-10-09T00:00:00Z","timestamp":1318118400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,10,9]]},"DOI":"10.1145\/2039370.2039405","type":"proceedings-article","created":{"date-parts":[[2011,10,11]],"date-time":"2011-10-11T14:29:11Z","timestamp":1318343351000},"page":"217-226","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["Optimal memory controller placement for chip multiprocessor"],"prefix":"10.1145","author":[{"given":"Thomas Canhao","family":"Xu","sequence":"first","affiliation":[{"name":"Turku Center for Computer Science (TUCS), Turku, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pasi","family":"Liljeberg","sequence":"additional","affiliation":[{"name":"University of Turku, Turku, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hannu","family":"Tenhunen","sequence":"additional","affiliation":[{"name":"University of Turku, Turku, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,10,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555810"},{"key":"e_1_3_2_1_2_1","unstructured":"AMD. The amd opteron 6000 series platform May 2010. http:\/\/www.amd.com\/-us\/products\/server\/processors\/6000-series-platform\/pages\/6000-series-platform.aspx.  AMD. The amd opteron 6000 series platform May 2010. http:\/\/www.amd.com\/-us\/products\/server\/processors\/6000-series-platform\/pages\/6000-series-platform.aspx."},{"key":"e_1_3_2_1_3_1","volume-title":"The international technology roadmap for semiconductors (itrs)","author":"S. I. Association","year":"2007","unstructured":"S. I. Association . The international technology roadmap for semiconductors (itrs) , 2007 . http:\/\/www.itrs.net\/Links\/2007ITRS\/Home2007.htm. S. I. Association. The international technology roadmap for semiconductors (itrs), 2007. http:\/\/www.itrs.net\/Links\/2007ITRS\/Home2007.htm."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854314"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_6_1","unstructured":"T. Corporation August 2010. http:\/\/www.tilera.com.  T. Corporation August 2010. http:\/\/www.tilera.com."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_8_1","volume-title":"June","author":"Global H.","year":"2010","unstructured":"H. Global . Ddr 2 memory controller ip core for fpga and asic , June 2010 . http:\/\/www.hitechglobal.com\/ipcores\/ddr2controller.htm. H. Global. Ddr 2 memory controller ip core for fpga and asic, June 2010. http:\/\/www.hitechglobal.com\/ipcores\/ddr2controller.htm."},{"key":"e_1_3_2_1_9_1","volume-title":"Hot chips","author":"BM.","year":"2009","unstructured":"I BM. Ibm power 7 processor. In Hot chips 2009 , August 2009. IBM. Ibm power 7 processor. In Hot chips 2009, August 2009."},{"volume-title":"Intel core i7 processor extreme edition and intel core i7 processor datasheet","year":"2008","key":"e_1_3_2_1_10_1","unstructured":"Intel. Intel core i7 processor extreme edition and intel core i7 processor datasheet , volume 1 , December 2008 . http:\/\/download.intel.com\/design\/processor\/datashts-\/320834.pdf. Intel. Intel core i7 processor extreme edition and intel core i7 processor datasheet, volume 1, December 2008. http:\/\/download.intel.com\/design\/processor\/datashts-\/320834.pdf."},{"volume-title":"May","year":"2010","key":"e_1_3_2_1_11_1","unstructured":"Intel. Single-chip cloud computer , May 2010 . http:\/\/techresearch.intel.com\/-articles\/Tera-Scale\/1826.htm. Intel. Single-chip cloud computer, May 2010. http:\/\/techresearch.intel.com\/-articles\/Tera-Scale\/1826.htm."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874721"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/605432.605420"},{"key":"e_1_3_2_1_14_1","first-page":"1","volume-title":"Proceedings of the 16th HPCA","author":"Kim Y.","year":"2010","unstructured":"Y. Kim , D. Han , O. Mutlu , and M. Harchol-Balter . Atlas: A scalable and high-performance scheduling algorithm for multiple memory controllers . In Proceedings of the 16th HPCA , pages 1 -- 12 , 2010 . Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter. Atlas: A scalable and high-performance scheduling algorithm for multiple memory controllers. In Proceedings of the 16th HPCA, pages 1 --12, 2010."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.31"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382128"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393988"},{"key":"e_1_3_2_1_20_1","first-page":"20","author":"Shyamkumar T.","year":"2008","unstructured":"T. Shyamkumar , M. Naveen , A. J. Ho , and J. N. P . Cacti 5.1. Technical Report HPL- 2008 -- 20 , HP Labs. T. Shyamkumar, M. Naveen, A. J. Ho, and J. N. P. Cacti 5.1. Technical Report HPL-2008--20, HP Labs.","journal-title":"Cacti 5.1. Technical Report HPL-"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/800255.810659"},{"key":"e_1_3_2_1_22_1","unstructured":"TPC. Tpc-h decision support benchmark. http:\/\/www.tpc.org\/tpch\/.  TPC. Tpc-h decision support benchmark. http:\/\/www.tpc.org\/tpch\/."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523067"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373606"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.89"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"}],"event":{"name":"ESWeek '11: Seventh Embedded Systems Week","sponsor":["CEDA","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"],"location":"Taipei Taiwan","acronym":"ESWeek '11"},"container-title":["Proceedings of the seventh IEEE\/ACM\/IFIP international conference on Hardware\/software codesign and system synthesis"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2039370.2039405","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2039370.2039405","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:54:36Z","timestamp":1750240476000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2039370.2039405"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10,9]]},"references-count":26,"alternative-id":["10.1145\/2039370.2039405","10.1145\/2039370"],"URL":"https:\/\/doi.org\/10.1145\/2039370.2039405","relation":{},"subject":[],"published":{"date-parts":[[2011,10,9]]},"assertion":[{"value":"2011-10-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}