{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:02:22Z","timestamp":1761580942280,"version":"3.41.0"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2011,12,1]],"date-time":"2011-12-01T00:00:00Z","timestamp":1322697600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/D07908X\/1EP\/G015740\/1"],"award-info":[{"award-number":["EP\/D07908X\/1EP\/G015740\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2011,12]]},"abstract":"<jats:p>The design and implementation of globally asynchronous locally synchronous systems-on-chip is a challenging activity. The large size and complexity of the systems require the use of computer-aided design (CAD) tools but, unfortunately, most tools do not work adequately with asynchronous circuits. This article describes the successful design and implementation of SpiNNaker, a GALS multicore system-on-chip. The process was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way that allows the tools to complete their tasks successfully. A first test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modified to cope with the increased complexity of the SpiNNaker SoC. SpiNNaker chips were delivered in May 2011 and were also fully operational, and the interconnect requirements were met.<\/jats:p>","DOI":"10.1145\/2043643.2043647","type":"journal-article","created":{"date-parts":[[2011,12,13]],"date-time":"2011-12-13T15:45:47Z","timestamp":1323791147000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":34,"title":["SpiNNaker"],"prefix":"10.1145","volume":"7","author":[{"given":"Luis A.","family":"Plana","sequence":"first","affiliation":[{"name":"The University of Manchester"}]},{"given":"David","family":"Clark","sequence":"additional","affiliation":[{"name":"The University of Manchester"}]},{"given":"Simon","family":"Davidson","sequence":"additional","affiliation":[{"name":"The University of Manchester"}]},{"given":"Steve","family":"Furber","sequence":"additional","affiliation":[{"name":"The University of Manchester"}]},{"given":"Jim","family":"Garside","sequence":"additional","affiliation":[{"name":"The University of Manchester"}]},{"given":"Eustace","family":"Painkras","sequence":"additional","affiliation":[{"name":"The University of Manchester"}]},{"given":"Jeffrey","family":"Pepper","sequence":"additional","affiliation":[{"name":"The University of Manchester"}]},{"given":"Steve","family":"Temple","sequence":"additional","affiliation":[{"name":"The University of Manchester"}]},{"given":"John","family":"Bainbridge","sequence":"additional","affiliation":[{"name":"Sil\u00edstix"}]}],"member":"320","published-online":{"date-parts":[[2011,12]]},"reference":[{"issue":"0","key":"e_1_2_1_1_1","article-title":"Advanced microcontroller bus architecture AMBA specification","volume":"2","author":"ARM.","year":"1999","unstructured":"ARM. 1999 . Advanced microcontroller bus architecture AMBA specification , Rev. 2 . 0 . http:\/\/www.arm.com\/products\/solutions\/AMBAHomePage.html. ARM. 1999. Advanced microcontroller bus architecture AMBA specification, Rev. 2.0. http:\/\/www.arm.com\/products\/solutions\/AMBAHomePage.html.","journal-title":"Rev."},{"issue":"0","key":"e_1_2_1_2_1","article-title":"Advanced microcontroller bus architecture AMBA 3 APB protocol specification","volume":"1","author":"ARM.","year":"2004","unstructured":"ARM. 2004 a. Advanced microcontroller bus architecture AMBA 3 APB protocol specification , Rev. 1 . 0 . http:\/\/www.arm.com\/products\/solutions\/AMBAHomePage.html. ARM. 2004a. Advanced microcontroller bus architecture AMBA 3 APB protocol specification, Rev. 1.0. http:\/\/www.arm.com\/products\/solutions\/AMBAHomePage.html.","journal-title":"Rev."},{"issue":"0","key":"e_1_2_1_3_1","article-title":"Advanced microcontroller bus architecture AMBA AXI protocol specification","volume":"1","author":"ARM.","year":"2004","unstructured":"ARM. 2004 b. Advanced microcontroller bus architecture AMBA AXI protocol specification , Rev. 1 . 0 . http:\/\/www.arm.com\/products\/solutions\/AMBAHomePage.html. ARM. 2004b. Advanced microcontroller bus architecture AMBA AXI protocol specification, Rev. 1.0. http:\/\/www.arm.com\/products\/solutions\/AMBAHomePage.html.","journal-title":"Rev."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.1044296"},{"volume-title":"Proceedings of the International Symposium on Asynchronous Circuits and Systems. IEEE Computer Society Press","author":"Bainbridge W. J.","key":"e_1_2_1_5_1","unstructured":"Bainbridge , W. J. , Toms , W. B. , Edwards , D. A. , and Furber , S. B . 2003. Delay-insensitive, point-to-point interconnect using m-of-n codes . In Proceedings of the International Symposium on Asynchronous Circuits and Systems. IEEE Computer Society Press , Los Alamitos, CA, 132--140. Bainbridge, W. J., Toms, W. B., Edwards, D. A., and Furber, S. B. 2003. Delay-insensitive, point-to-point interconnect using m-of-n codes. In Proceedings of the International Symposium on Asynchronous Circuits and Systems. IEEE Computer Society Press, Los Alamitos, CA, 132--140."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1132952.1132953"},{"volume-title":"Proceedings of the FMGALS Workshop at the 12th International FME Symposium.","author":"G\u00fcrkaynak F. K.","key":"e_1_2_1_7_1","unstructured":"G\u00fcrkaynak , F. K. , Oetiker , S. , Villiger , T. , Felber , N. , Kaeslin , H. , and Fichtner , W . 2003. On the GALS design methodology of ETH Zurich . In Proceedings of the FMGALS Workshop at the 12th International FME Symposium. G\u00fcrkaynak, F. K., Oetiker, S., Villiger, T., Felber, N., Kaeslin, H., and Fichtner, W. 2003. On the GALS design methodology of ETH Zurich. In Proceedings of the FMGALS Workshop at the 12th International FME Symposium."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2010.112"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1018139"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.1268991"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2010691"},{"volume-title":"Proceedings of the ACM\/IEEE International Symposium on Networks-on-Chip. IEEE Computer Society Press","author":"Plana L. A.","key":"e_1_2_1_12_1","unstructured":"Plana , L. A. , Bainbridge , J. , Furber , S. , Salisbury , S. , Shi , Y. , and Wu , J . 2008. An on-chip and inter-chip communications network for the SpiNNaker massively--parallel neural net simulator . In Proceedings of the ACM\/IEEE International Symposium on Networks-on-Chip. IEEE Computer Society Press , Los Alamitos, CA, 215--216. Plana, L. A., Bainbridge, J., Furber, S., Salisbury, S., Shi, Y., and Wu, J. 2008. An on-chip and inter-chip communications network for the SpiNNaker massively--parallel neural net simulator. In Proceedings of the ACM\/IEEE International Symposium on Networks-on-Chip. IEEE Computer Society Press, Los Alamitos, CA, 215--216."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.149"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2007.11"},{"volume-title":"Introduction to VLSI Systems","author":"Seitz C. L.","key":"e_1_2_1_15_1","unstructured":"Seitz , C. L. 1980. System timing . In Introduction to VLSI Systems , C. A. Mead and L. A. Conway Eds., Addison-Wesley, Reading , MA (Chapter 7). Seitz, C. L. 1980. System timing. In Introduction to VLSI Systems, C. A. Mead and L. A. Conway Eds., Addison-Wesley, Reading, MA (Chapter 7)."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514025"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1561\/1000000006"},{"volume-title":"Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE\u201910)","author":"Thonnart Y.","key":"e_1_2_1_18_1","unstructured":"Thonnart , Y. , Vivet , P. , and Clermidy , F . 2010. A fully-asynchronous low-power framework for GALS NOC integration . In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE\u201910) . 33--38. Thonnart, Y., Vivet, P., and Clermidy, F. 2010. A fully-asynchronous low-power framework for GALS NOC integration. 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IEEE Computer Society Press, Los Alamitos, CA, 243--246."}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2043643.2043647","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2043643.2043647","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:54:19Z","timestamp":1750240459000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2043643.2043647"}},"subtitle":["Design and Implementation of a GALS Multicore System-on-Chip"],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":20,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2011,12]]}},"alternative-id":["10.1145\/2043643.2043647"],"URL":"https:\/\/doi.org\/10.1145\/2043643.2043647","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2011,12]]},"assertion":[{"value":"2011-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-12-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}