{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,16]],"date-time":"2026-04-16T10:41:19Z","timestamp":1776336079008,"version":"3.51.2"},"reference-count":74,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2011,11,1]],"date-time":"2011-11-01T00:00:00Z","timestamp":1320105600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2011,11]]},"abstract":"<jats:p>Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. Massively parallel embedded systems specifically deal with the optimized usage of such hardware resources to efficiently execute their functionalities. The design of these systems mainly relies on the following challenging issues: first, how to deal with the parallelism in order to increase the performance; second, how to abstract their implementation details in order to manage their complexity; third, how to refine these abstract representations in order to produce efficient implementations.<\/jats:p>\n          <jats:p>\n            This article presents the\n            <jats:sc>Gaspard<\/jats:sc>\n            design framework for massively parallel embedded systems as a solution to the preceding issues.\n            <jats:sc>Gaspard<\/jats:sc>\n            uses the repetitive Model of Computation (MoC), which offers a powerful expression of the regular parallelism available in both system functionality and architecture. Embedded systems are designed at a high abstraction level with the MARTE (Modeling and Analysis of Real-time and Embedded systems) standard profile, in which our repetitive MoC is described by the so-called Repetitive Structure Modeling (RSM) package. Based on the Model-Driven Engineering (MDE) paradigm, MARTE models are refined towards lower abstraction levels, which make possible the design space exploration. By combining all these capabilities,\n            <jats:sc>Gaspard<\/jats:sc>\n            allows the designers to automatically generate code for formal verification, simulation and hardware synthesis from high-level specifications of high-performance embedded systems. Its effectiveness is demonstrated with the design of an embedded system for a multimedia application.\n          <\/jats:p>","DOI":"10.1145\/2043662.2043663","type":"journal-article","created":{"date-parts":[[2011,11,30]],"date-time":"2011-11-30T13:58:46Z","timestamp":1322661526000},"page":"1-36","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":68,"title":["A Model-Driven Design Framework for Massively Parallel Embedded Systems"],"prefix":"10.1145","volume":"10","author":[{"given":"Abdoulaye","family":"Gamati\u00e9","sequence":"first","affiliation":[{"name":"LIFL Lab and INRIA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S\u00e9bastien","family":"Le Beux","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique Montr\u00e9al"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"\u00c9ric","family":"Piel","sequence":"additional","affiliation":[{"name":"Technical University of Delft"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rabie","family":"Ben Atitallah","sequence":"additional","affiliation":[{"name":"UVHC, LAMIH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anne","family":"Etien","sequence":"additional","affiliation":[{"name":"LIFL Lab and INRIA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philippe","family":"Marquet","sequence":"additional","affiliation":[{"name":"LIFL Lab and INRIA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Luc","family":"Dekeyser","sequence":"additional","affiliation":[{"name":"LIFL Lab and INRIA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MBD-MOMPES.2006.8"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/207110.207134"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/384196.384210"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1193228"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/1025127.1025992"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the Canadian Conference on Electrical and Computer Engineering (CCECE\u201906)","author":"Ben Atitallah A."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2007.21"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the IEEE International SoC Conference (SoCC\u201907)","author":"Ben Atitallah R."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.805826"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the 20th IEEE Norchip Conference.","author":"Bj\u00f6rklund D."},{"key":"e_1_2_1_11_1","unstructured":"Borland. 2007. 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