{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,14]],"date-time":"2026-03-14T06:37:31Z","timestamp":1773470251951,"version":"3.50.1"},"reference-count":34,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2011,12,1]],"date-time":"2011-12-01T00:00:00Z","timestamp":1322697600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2011,12]]},"abstract":"<jats:p>\n            The VPR toolset has been widely used in FPGA architecture and CAD research, but has not evolved over the past decade. This article describes and illustrates the use of a new version of the toolset that includes four new features: first, it supports a broad range of\n            <jats:italic>single-driver<\/jats:italic>\n            routing architectures, which have superior architectural and electrical properties over the prior multidriver approach (and which is now employed in the majority of FPGAs sold). Second, it can now model, for placement and routing a heterogeneous selection of hard logic blocks. This is a key (but not final) step toward the incluion of blocks such as memory and multipliers. Third, we provide optimized\n            <jats:italic>electrical<\/jats:italic>\n            models for a wide range of architectures in different process technologies, including a range of area-delay trade-offs for each single architecture. Finally, to maintain robustness and support future development the release includes a set of regression tests for the software.\n          <\/jats:p>\n          <jats:p>To illustrate the use of the new features, we explore several architectural issues: the FPGA area efficiency versus logic block granularity, the effect of single-driver routing, and a simple use of the heterogeneity to explore the impact of hard multipliers on wiring track count.<\/jats:p>","DOI":"10.1145\/2068716.2068718","type":"journal-article","created":{"date-parts":[[2011,12,27]],"date-time":"2011-12-27T15:22:22Z","timestamp":1324999342000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":58,"title":["VPR 5.0"],"prefix":"10.1145","volume":"4","author":[{"given":"Jason","family":"Luu","sequence":"first","affiliation":[{"name":"University of Toronto, Canada"}]},{"given":"Ian","family":"Kuon","sequence":"additional","affiliation":[{"name":"University of Toronto, Canada"}]},{"given":"Peter","family":"Jamieson","sequence":"additional","affiliation":[{"name":"University of Toronto, Canada"}]},{"given":"Ted","family":"Campbell","sequence":"additional","affiliation":[{"name":"University of Toronto, Canada"}]},{"given":"Andy","family":"Ye","sequence":"additional","affiliation":[{"name":"University of Toronto, Canada"}]},{"given":"Wei Mark","family":"Fang","sequence":"additional","affiliation":[{"name":"University of Toronto, Canada"}]},{"given":"Kenneth","family":"Kent","sequence":"additional","affiliation":[{"name":"University of New Brunswick, Canada"}]},{"given":"Jonathan","family":"Rose","sequence":"additional","affiliation":[{"name":"University of Toronto, Canada"}]}],"member":"320","published-online":{"date-parts":[[2011,12,28]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"e_1_2_1_2_1","volume-title":"Datasheet: Flex 10k embedded programmable logic family","author":"Altera","year":"1995","unstructured":"Altera . 1995 . Datasheet: Flex 10k embedded programmable logic family . http:\/\/web.mit.edu\/6.111\/www\/s2004\/LABS\/dsflok.pdf. Altera. 1995. Datasheet: Flex 10k embedded programmable logic family. http:\/\/web.mit.edu\/6.111\/www\/s2004\/LABS\/dsflok.pdf."},{"key":"e_1_2_1_3_1","unstructured":"Altera. 2007. Cyclone III device handbook. ver. CIII5V1-1.2 http:\/\/www.altera.com\/literature\/hb\/cyc3\/cyclone3_handbook.pdf.  Altera. 2007. Cyclone III device handbook. ver. CIII5V1-1.2 http:\/\/www.altera.com\/literature\/hb\/cyc3\/cyclone3_handbook.pdf."},{"key":"e_1_2_1_4_1","unstructured":"Altera. 2008. Stratix IV device handbook version SIV5V1-1.1. http:\/\/www.altera.com\/literature\/hb\/stratix-iv\/stratix4_handbook.pdf.  Altera. 2008. Stratix IV device handbook version SIV5V1-1.1. http:\/\/www.altera.com\/literature\/hb\/stratix-iv\/stratix4_handbook.pdf."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117204"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications.","author":"Betz V.","unstructured":"Betz , V. and Rose , J . 1997. VPR: A new packing, placement and routing tool for FPGA research . In Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. Betz, V. and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.655177"},{"key":"e_1_2_1_8_1","doi-asserted-by":"crossref","unstructured":"Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers.   Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers.","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277221"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference. 7.4.1--7.4.5.","author":"He J.","unstructured":"He , J. and Rose , J . 1993. Advantages of heterogeneous logic block architectures for FPGAs . In Proceedings of the IEEE Custom Integrated Circuits Conference. 7.4.1--7.4.5. He, J. and Rose, J. 1993. Advantages of heterogeneous logic block architectures for FPGAs. In Proceedings of the IEEE Custom Integrated Circuits Conference. 7.4.1--7.4.5."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_2_1_13_1","unstructured":"ITRS. 2007. International Technology Roadmap for Semiconductors 2007 Ed. http:\/\/www.itrs. net\/reports.html.  ITRS. 2007. International Technology Roadmap for Semiconductors 2007 Ed. http:\/\/www.itrs. net\/reports.html."},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications. 305--310","author":"Jamieson P.","unstructured":"Jamieson , P. and Rose , J . 2005. A verilog RTL synthesis tool for heterogeneous FPGAs . In Proceedings of the International Conference on Field Programmable Logic and Applications. 305--310 . Jamieson, P. and Rose, J. 2005. A verilog RTL synthesis tool for heterogeneous FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications. 305--310."},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the International Conference on Field-Programmable Technology. 57--64","author":"Jamieson P.","unstructured":"Jamieson , P. and Rose , J . 2007. Architecting hard crossbars on FPGAs and increasing their area efficiency with shadow clusters . In Proceedings of the International Conference on Field-Programmable Technology. 57--64 . Jamieson, P. and Rose, J. 2007. Architecting hard crossbars on FPGAs and increasing their area efficiency with shadow clusters. In Proceedings of the International Conference on Field-Programmable Technology. 57--64."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508165"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344695"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391671"},{"key":"e_1_2_1_19_1","volume-title":"Proceedings of the IEEE International Conference on Field-Programmable Technology. 41--48","author":"Lemieux G.","unstructured":"Lemieux , G. , Lee , E. , Tom , M. , and Yu , A . 2004. Directional and single-driver wires in FPGA interconnect . In Proceedings of the IEEE International Conference on Field-Programmable Technology. 41--48 . Lemieux, G., Lee, E., Tom, M., and Yu, A. 2004. Directional and single-driver wires in FPGA interconnect. In Proceedings of the IEEE International Conference on Field-Programmable Technology. 41--48."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360299"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611821"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059881"},{"key":"e_1_2_1_28_1","volume-title":"et al","author":"Sentovich E. M.","year":"1992","unstructured":"Sentovich , E. M. et al . 1992 . SIS : A system for sequential circuit synthesis. Tech. rep. UCB\/ERL M92\/41, Electronics Research Lab, University of California , Berkeley, CA. Sentovich, E. M. et al. 1992. SIS: A system for sequential circuit synthesis. Tech. rep. UCB\/ERL M92\/41, Electronics Research Lab, University of California, Berkeley, CA."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508156"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.859485"},{"key":"e_1_2_1_32_1","unstructured":"World Wide Web Consortium. 2008. Extensible markup language (xml). http:\/\/www.w3.org\/XML\/.  World Wide Web Consortium. 2008. Extensible markup language (xml). http:\/\/www.w3.org\/XML\/."},{"key":"e_1_2_1_33_1","volume-title":"Datasheet: Virtex 2.5 v field programmable gate arrays","author":"Xilinx","year":"2001","unstructured":"Xilinx . 2001 . Datasheet: Virtex 2.5 v field programmable gate arrays . http:\/\/www.gb.nrao.edu\/gbt\/MC\/GBTprojects\/pulsarSupport\/PulsarSplgotCard\/FPGA.pdf. Xilinx. 2001. Datasheet: Virtex 2.5 v field programmable gate arrays. http:\/\/www.gb.nrao.edu\/gbt\/MC\/GBTprojects\/pulsarSupport\/PulsarSplgotCard\/FPGA.pdf."},{"key":"e_1_2_1_34_1","unstructured":"Xilinx. 2008a. Spartan-3A FPGA family: Data sheet. Ver. 1.0 http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds529.pdf.  Xilinx. 2008a. Spartan-3A FPGA family: Data sheet. Ver. 1.0 http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds529.pdf."},{"key":"e_1_2_1_35_1","unstructured":"Xilinx. 2008b. Virtex-5 user guide. UG190 (v4.0) http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug190.pdf.  Xilinx. 2008b. Virtex-5 user guide. UG190 (v4.0) http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug190.pdf."},{"key":"e_1_2_1_36_1","first-page":"942","article-title":"FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines","volume":"5","author":"Young S. P.","year":"1999","unstructured":"Young , S. P. , Bauer , T. J. , Chaudhary , K. , and Krishnamurthy , S. 1999 . FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines . US Patent 5 , 942 ,913. Young, S. P., Bauer, T. J., Chaudhary, K., and Krishnamurthy, S. 1999. FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines. US Patent 5,942,913.","journal-title":"US Patent"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2068716.2068718","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2068716.2068718","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:54:24Z","timestamp":1750240464000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2068716.2068718"}},"subtitle":["FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling"],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":34,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2011,12]]}},"alternative-id":["10.1145\/2068716.2068718"],"URL":"https:\/\/doi.org\/10.1145\/2068716.2068718","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,12]]},"assertion":[{"value":"2009-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-12-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}