{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,20]],"date-time":"2025-08-20T12:21:42Z","timestamp":1755692502245,"version":"3.41.0"},"reference-count":29,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2011,12,1]],"date-time":"2011-12-01T00:00:00Z","timestamp":1322697600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2011,12]]},"abstract":"<jats:p>\n            Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. This article considers enhancements to a traditional LUT-based mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to\n            <jats:italic>k<\/jats:italic>\n            variables; specifically, the logic block is a partial LUT, but it possesses more inputs than a typical LUT. An analysis of the logic block is presented, and techniques for postmapping area recovery and timing-driven buffer insertion are also described. Numerical results are put forth which substantiate the efficacy of the proposed methods using real circuits mapped to a commercial FPGA architecture.\n          <\/jats:p>","DOI":"10.1145\/2068716.2068721","type":"journal-article","created":{"date-parts":[[2011,12,27]],"date-time":"2011-12-27T15:22:22Z","timestamp":1324999342000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["FPGA technology mapping with encoded libraries and staged priority cuts"],"prefix":"10.1145","volume":"4","author":[{"given":"Andrew","family":"Kennings","sequence":"first","affiliation":[{"name":"Actel Corporation, Mountain View, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kristofer","family":"Vorwerk","sequence":"additional","affiliation":[{"name":"Actel Corporation, Mountain View, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arun","family":"Kundu","sequence":"additional","affiliation":[{"name":"Actel Corporation, Mountain View, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Val","family":"Pevzner","sequence":"additional","affiliation":[{"name":"Actel Corporation, Mountain View, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andy","family":"Fox","sequence":"additional","affiliation":[{"name":"Actel Corporation, Mountain View, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2011,12,28]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065681"},{"key":"e_1_2_1_2_1","unstructured":"Actel Corporation. 2005. Axcelerator family FPGAs datasheet v2.6. Actel.  Actel Corporation. 2005. Axcelerator family FPGAs datasheet v2.6. Actel."},{"volume-title":"Stratix II Device Handbook","author":"Altera Corporation","key":"e_1_2_1_3_1","unstructured":"Altera Corporation . 2007. Stratix II Device Handbook , Vol. 1 . Altera . Altera Corporation. 2007. Stratix II Device Handbook, Vol. 1. Altera."},{"volume-title":"Proceedings of the Design, Automation and Test in Europe Conference (DATE). 1079--1084","author":"Chai D.","key":"e_1_2_1_4_1","unstructured":"Chai , D. and Kuelmann , A . 2006. Building a better Boolean matcher and symmetry detector . In Proceedings of the Design, Automation and Test in Europe Conference (DATE). 1079--1084 . Chai, D. and Kuelmann, A. 2006. Building a better Boolean matcher and symmetry detector. In Proceedings of the Design, Automation and Test in Europe Conference (DATE). 1079--1084."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233531"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382677"},{"volume-title":"Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA).","author":"Cho S.","key":"e_1_2_1_7_1","unstructured":"Cho , S. , Chatterjee , S. , Mishchenko , A. , and Brayton , R . 2007. Efficient FPGA mapping using priority cuts . In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA). Cho, S., Chatterjee, S., Mishchenko, A., and Brayton, R. 2007. Efficient FPGA mapping using priority cuts. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA)."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/233539.233540"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216944"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"volume-title":"Proceedings of the EUROMICRO Conference. 130--137","author":"Gunther W.","key":"e_1_2_1_12_1","unstructured":"Gunther , W. and Drechsler , R . 2000. ACTion: Combining logic synthesis and technology mapping for mux based FPGAs . In Proceedings of the EUROMICRO Conference. 130--137 . Gunther, W. and Drechsler, R. 2000. ACTion: Combining logic synthesis and technology mapping for mux based FPGAs. In Proceedings of the EUROMICRO Conference. 130--137."},{"volume-title":"Proceedings of the International Conference on Computer Aided Design (ICCAD). 188--193","author":"Hu Y.","key":"e_1_2_1_13_1","unstructured":"Hu , Y. , Das , S. , Trimberger , S. , and He , L . 2007a. Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates . In Proceedings of the International Conference on Computer Aided Design (ICCAD). 188--193 . Hu, Y., Das, S., Trimberger, S., and He, L. 2007a. Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. In Proceedings of the International Conference on Computer Aided Design (ICCAD). 188--193."},{"volume-title":"Proceedings of the International Conference on Computer Aided Design (ICCAD). 350--353","author":"Hu Y.","key":"e_1_2_1_14_1","unstructured":"Hu , Y. , Shih , V. , Majumdar , R. , and He , L . 2007b. Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping . In Proceedings of the International Conference on Computer Aided Design (ICCAD). 350--353 . Hu, Y., Shih, V., Majumdar, R., and He, L. 2007b. Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. In Proceedings of the International Conference on Computer Aided Design (ICCAD). 350--353."},{"volume-title":"Proceedings of the International Workshop on Logic and Synthesis (IWLS).","author":"Hu Y.","key":"e_1_2_1_15_1","unstructured":"Hu , Y. , Shih , V. , Majumdar , R. , and He , L . 2007c. Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping . In Proceedings of the International Workshop on Logic and Synthesis (IWLS). Hu, Y., Shih, V., Majumdar, R., and He, L. 2007c. Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. In Proceedings of the International Workshop on Logic and Synthesis (IWLS)."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30117-2_16"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344680"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508151"},{"key":"e_1_2_1_19_1","first-page":"2331","article-title":"Logic decomposition during technology mapping","volume":"16","author":"Lehman E.","year":"1997","unstructured":"Lehman , E. , Watanabe , Y. , Grodstein , J. , and Harkness , H. 1997 . Logic decomposition during technology mapping . Trans. Comput.-Aided Des. 16 , 8, 2331 -- 2340 . Lehman, E., Watanabe, Y., Grodstein, J., and Harkness, H. 1997. Logic decomposition during technology mapping. Trans. Comput.-Aided Des. 16, 8, 2331--2340.","journal-title":"Trans. Comput.-Aided Des."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065693"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882119"},{"volume-title":"Proceedings of the TENCON Conference. 419--422","author":"Marik M.","key":"e_1_2_1_23_1","unstructured":"Marik , M. and Pal , A . 2004. Logic synthesis and technology mapping of mux-based FPGAs for high performance and low power . In Proceedings of the TENCON Conference. 419--422 . Marik, M. and Pal, A. 2004. Logic synthesis and technology mapping of mux-based FPGAs for high performance and low power. In Proceedings of the TENCON Conference. 419--422."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"key":"e_1_2_1_25_1","unstructured":"Mishchenko A. Chatterjee S. Jiang R. and Brayton R. K. 2005. FRAIGs: A unifying representation for logic synthesis and verification. Tech. rep. ERL University of California Berkeley.  Mishchenko A. Chatterjee S. Jiang R. and Brayton R. K. 2005. FRAIGs: A unifying representation for logic synthesis and verification. Tech. rep. ERL University of California Berkeley."},{"volume-title":"Proceedings of the International Conference on Computer Aided Design (ICCAD). 354--361","author":"Mishchenko A.","key":"e_1_2_1_26_1","unstructured":"Mishchenko , A. , Cho , S. , Chatterjee , S. , and Brayton , R . 2007b. Combinational and sequential mapping with priority cuts . In Proceedings of the International Conference on Computer Aided Design (ICCAD). 354--361 . Mishchenko, A., Cho, S., Chatterjee, S., and Brayton, R. 2007b. Combinational and sequential mapping with priority cuts. In Proceedings of the International Conference on Computer Aided Design (ICCAD). 354--361."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147034"},{"volume-title":"Proceedings of the Conference on Boolean Problems. 115--126","author":"Stankovi C, R. S.","key":"e_1_2_1_28_1","unstructured":"Stankovi C, R. S. , Astola , J. , and Steinbach , B . 2008. Former and recent work in classification of switching functions . In Proceedings of the Conference on Boolean Problems. 115--126 . Stankovi C, R. S., Astola, J., and Steinbach, B. 2008. Former and recent work in classification of switching functions. In Proceedings of the Conference on Boolean Problems. 115--126."},{"volume-title":"Proceedings of the International Conference on Computer Design (ICCD). 319--320","author":"Yi K.","key":"e_1_2_1_29_1","unstructured":"Yi , K. and Ohm , S. Y . 1999. A fast and exact cell matching method for mux-based FPGA technology mapping . In Proceedings of the International Conference on Computer Design (ICCD). 319--320 . Yi, K. and Ohm, S. Y. 1999. A fast and exact cell matching method for mux-based FPGA technology mapping. In Proceedings of the International Conference on Computer Design (ICCD). 319--320."}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2068716.2068721","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2068716.2068721","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:54:24Z","timestamp":1750240464000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2068716.2068721"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":29,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2011,12]]}},"alternative-id":["10.1145\/2068716.2068721"],"URL":"https:\/\/doi.org\/10.1145\/2068716.2068721","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2011,12]]},"assertion":[{"value":"2009-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-12-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}