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First, we present an ordered depth-first layout and a traversal architecture using this layout to reduce the required memory bandwidth. Second, we propose a three-phase ray-triangle intersection architecture that takes advantage of early exit. Third, we propose a latency hiding architecture defined as the ray accumulation unit. Cycle-accurate simulation results indicate our architecture can achieve interactive distributed ray tracing.<\/jats:p>","DOI":"10.1145\/2070781.2024194","type":"journal-article","created":{"date-parts":[[2011,11,30]],"date-time":"2011-11-30T13:58:46Z","timestamp":1322661526000},"page":"1-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["T&amp;I engine"],"prefix":"10.1145","volume":"30","author":[{"given":"Jae-Ho","family":"Nah","sequence":"first","affiliation":[{"name":"Yonsei University, Korea"}]},{"given":"Jeong-Soo","family":"Park","sequence":"additional","affiliation":[{"name":"Yonsei University, Korea"}]},{"given":"Chanmin","family":"Park","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Korea"}]},{"given":"Jin-Woo","family":"Kim","sequence":"additional","affiliation":[{"name":"Yonsei University, Korea"}]},{"given":"Yun-Hye","family":"Jung","sequence":"additional","affiliation":[{"name":"Yonsei University, Korea"}]},{"given":"Woo-Chan","family":"Park","sequence":"additional","affiliation":[{"name":"Sejong University, Korea"}]},{"given":"Tack-Don","family":"Han","sequence":"additional","affiliation":[{"name":"Yonsei University, Korea"}]}],"member":"320","published-online":{"date-parts":[[2011,12,12]]},"reference":[{"volume-title":"HPG' 10: Proceedings of the Conference on High Performance Graphics, 113--122","author":"Aila T.","key":"e_1_2_1_1_1","unstructured":"Aila , T. , and Karras , T . 2010. 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