{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:25:20Z","timestamp":1750307120562,"version":"3.41.0"},"reference-count":15,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2012,1]]},"abstract":"<jats:p>Electromigration and voltage drop (IR-drop) are two major reliability issues in modern IC design. Electromigration gradually creates permanently open or short circuits due to excessive current densities; IR-drop causes insufficient power supply, thus degrading performance or even inducing functional errors because of nonzero wire resistance. Both types of failure can be triggered by insufficient wire widths. Although expanding the wire width alleviates electromigration and IR-drop, unlimited expansion not only increases the routing cost, but may also be infeasible due to the limited routing resource. In addition, electromigration and IR-drop manifest mainly in the power\/ground (P\/G) network. Therefore, taking wire widths into consideration is desirable to prevent electromigration and IR-drop at P\/G routing. Unlike mature digital IC designs, P\/G routing in analog ICs has not yet been well studied. In a conventional design, analog designers manually route P\/G networks by implementing greedy strategies. However, the growing scale of analog ICs renders manual routing inefficient, and the greedy strategies may be ineffective when electromigration and IR-drop are considered. This study distances itself from conventional manual design and proposes an automatic analog P\/G router that considers electromigration and IR-drops. First, employing transportation formulation, this article constructs an electromigration-aware rectilinear Steiner tree with the minimum routing cost. Second, without changing the solution quality, wires are bundled to release routing space for enhancing routability and relaxing congestion. A wire width extension method is subsequently adopted to reduce wire resistance for IR-drop safety. Compared with high-tech designs, the proposed approach achieves equally optimal solutions for electromigration avoidance, with superior efficiencies. Furthermore, via industrial design, experimental results also show the effectiveness and efficiency of the proposed algorithm for electromigration prevention and IR-drop reduction.<\/jats:p>","DOI":"10.1145\/2071356.2071362","type":"journal-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T14:49:20Z","timestamp":1328021360000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Reliability-Driven Power\/Ground Routing for Analog ICs"],"prefix":"10.1145","volume":"17","author":[{"given":"Jing-Wei","family":"Lin","sequence":"first","affiliation":[{"name":"National Cheng Kung University"}]},{"given":"Tsung-Yi","family":"Ho","sequence":"additional","affiliation":[{"name":"National Cheng Kung University"}]},{"given":"Iris Hui-Ru","family":"Jiang","sequence":"additional","affiliation":[{"name":"National Chiao Tung University"}]}],"member":"320","published-online":{"date-parts":[[2012,1]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1109\/T-ED.1969.16754"},{"unstructured":"Cormen T. H. Leiserson C. E. Rivest R. L. and Stein C. 2009. Introduction to Algorithms 3rd Ed. MIT Press. Cormen T. H. Leiserson C. E. Rivest R. L. and Stein C. 2009. Introduction to Algorithms 3rd Ed. MIT Press.","key":"e_1_2_1_2_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1145\/74382.74529"},{"doi-asserted-by":"publisher","key":"e_1_2_1_4_1","DOI":"10.1109\/43.46785"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1145\/1735023.1735064"},{"doi-asserted-by":"publisher","key":"e_1_2_1_6_1","DOI":"10.1145\/1123008.1123017"},{"doi-asserted-by":"publisher","key":"e_1_2_1_7_1","DOI":"10.1145\/1119772.1119946"},{"doi-asserted-by":"publisher","key":"e_1_2_1_8_1","DOI":"10.1109\/TCAD.2008.917583"},{"doi-asserted-by":"publisher","key":"e_1_2_1_9_1","DOI":"10.1145\/201310.201328"},{"doi-asserted-by":"publisher","key":"e_1_2_1_10_1","DOI":"10.1145\/1233501.1233596"},{"doi-asserted-by":"publisher","key":"e_1_2_1_11_1","DOI":"10.1287\/opre.17.1.187"},{"doi-asserted-by":"publisher","key":"e_1_2_1_12_1","DOI":"10.1145\/1403375.1403477"},{"volume-title":"Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD\u201907)","author":"Todri A.","unstructured":"Todri , A. , Marek-Sadowska , M. , and Chang , S . -C. 2007. Analysis and optimization of power-gated ICS with multiple power gating configurations . In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD\u201907) . IEEE, Los Alamitos, CA, 783--790. Todri, A., Marek-Sadowska, M., and Chang, S.-C. 2007. Analysis and optimization of power-gated ICS with multiple power gating configurations. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD\u201907). IEEE, Los Alamitos, CA, 783--790.","key":"e_1_2_1_13_1"},{"key":"e_1_2_1_14_1","volume-title":"Operations Research Applications and Algorithms","author":"Winston W. L.","unstructured":"Winston , W. L. 2004. Operations Research Applications and Algorithms 4 th Ed., Thomsom Brooks\/Cole . Winston, W. L. 2004. Operations Research Applications and Algorithms 4th Ed., Thomsom Brooks\/Cole.","edition":"4"},{"volume-title":"Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS\u201908)","author":"Yan J.-T.","unstructured":"Yan , J.-T. and Chen , Z . -W. 2008. Electromigration-aware rectilinear Steiner tree construction for analog circuits . In Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS\u201908) . IEEE, Los Alamitos, CA, 1692--1695. Yan, J.-T. and Chen, Z.-W. 2008. Electromigration-aware rectilinear Steiner tree construction for analog circuits. In Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS\u201908). IEEE, Los Alamitos, CA, 1692--1695.","key":"e_1_2_1_15_1"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2071356.2071362","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2071356.2071362","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:48:24Z","timestamp":1750240104000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2071356.2071362"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":15,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,1]]}},"alternative-id":["10.1145\/2071356.2071362"],"URL":"https:\/\/doi.org\/10.1145\/2071356.2071362","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2012,1]]},"assertion":[{"value":"2011-01-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-01-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}