{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:26:54Z","timestamp":1750307214070,"version":"3.41.0"},"reference-count":16,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2011,12,19]],"date-time":"2011-12-19T00:00:00Z","timestamp":1324252800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2011,12,19]]},"abstract":"<jats:p>\n            This paper describes\n            <jats:italic>CoreSymphony<\/jats:italic>\n            , a cooperative and reconfigurable superscalar processor architecture that improves single-thread performance in chip multiprocessor. CoreSymphony enables some narrow-issue cores to be fused into a single wide-issue core. In this paper, we describe the problems associated with achieving the cooperative superscalar processor. We then describe techniques by which to overcome these problems. The evaluation results obtained using SPEC2006 benchmarks indicate that four-core fusion achieves 88% higher IPC than an individual core.\n          <\/jats:p>","DOI":"10.1145\/2082156.2082165","type":"journal-article","created":{"date-parts":[[2011,12,27]],"date-time":"2011-12-27T15:22:22Z","timestamp":1324999342000},"page":"32-37","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["CoreSymphony"],"prefix":"10.1145","volume":"39","author":[{"given":"Tomoyuki","family":"Nagatsuka","sequence":"first","affiliation":[{"name":"Tokyo Institute of Technology, Japan"}]},{"given":"Yoshito","family":"Sakaguchi","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology, Japan"}]},{"given":"Takayuki","family":"Matsumura","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology, Japan"}]},{"given":"Kenji","family":"Kise","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology, Japan"}]}],"member":"320","published-online":{"date-parts":[[2011,12,19]]},"reference":[{"issue":"3","key":"e_1_2_1_1_1","first-page":"67","article-title":"A Cooperative Superscalar Processor","volume":"3","author":"Wakasugi Yuhta","year":"2010","unstructured":"Yuhta Wakasugi , Yoshito Sakaguchi , and Kenji Kise . CoreSymphony : A Cooperative Superscalar Processor . IPSJ Transactions on Advanced Computing Systems , Vol. 3 , No. 3 , pp. 67 -- 87 , 2010 . Yuhta Wakasugi, Yoshito Sakaguchi, and Kenji Kise. CoreSymphony: A Cooperative Superscalar Processor. IPSJ Transactions on Advanced Computing Systems, Vol. 3, No. 3, pp. 67--87, 2010.","journal-title":"IPSJ Transactions on Advanced Computing Systems"},{"key":"e_1_2_1_2_1","unstructured":"Jim Held Jerry Bautista and Sean Koehl. From a Few Cores to Many: A Tera-Scale Computing Research Overview. white paper Intel http:\/\/download.intel.com\/research\/platform\/terascale\/terascale_overview_paper.pdf.  Jim Held Jerry Bautista and Sean Koehl. From a Few Cores to Many: A Tera-Scale Computing Research Overview. white paper Intel http:\/\/download.intel.com\/research\/platform\/terascale\/terascale_overview_paper.pdf."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250686"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555813"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.27"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1331699.1331733"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.65"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346182"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.491460"},{"key":"e_1_2_1_12_1","volume-title":"Englewood Cliffs","author":"Johonson Mike","year":"1990","unstructured":"Mike Johonson . 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A MIPS System Simulator SimMips for Education and Research of Computer Science. IPSJ Transactions on Advanced Computing Systems, Vol. 50, No. 11, pp. 2665--2676, 2009.","journal-title":"IPSJ Transactions on Advanced Computing Systems"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2082156.2082165","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2082156.2082165","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:06:42Z","timestamp":1750241202000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2082156.2082165"}},"subtitle":["an efficient reconfigurable multi-core architecture"],"short-title":[],"issued":{"date-parts":[[2011,12,19]]},"references-count":16,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2011,12,19]]}},"alternative-id":["10.1145\/2082156.2082165"],"URL":"https:\/\/doi.org\/10.1145\/2082156.2082165","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2011,12,19]]},"assertion":[{"value":"2011-12-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}