{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:26:54Z","timestamp":1750307214171,"version":"3.41.0"},"reference-count":5,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2011,12,19]],"date-time":"2011-12-19T00:00:00Z","timestamp":1324252800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2011,12,19]]},"DOI":"10.1145\/2082156.2082177","type":"journal-article","created":{"date-parts":[[2011,12,27]],"date-time":"2011-12-27T15:22:22Z","timestamp":1324999342000},"page":"82-85","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Parallelization of the channel width search for FPGA routing"],"prefix":"10.1145","volume":"39","author":[{"given":"Hiroomi","family":"Sawada","sequence":"first","affiliation":[{"name":"Kumamoto University, Kumamoto, Japan"}]},{"given":"Morihiro","family":"Kuga","sequence":"additional","affiliation":[{"name":"Kumamoto University, Kumamoto, Japan"}]},{"given":"Motoki","family":"Amagasaki","sequence":"additional","affiliation":[{"name":"Kumamoto University, Kumamoto, Japan"}]},{"given":"Masahiro","family":"Iida","sequence":"additional","affiliation":[{"name":"Kumamoto University, Kumamoto, Japan"}]},{"given":"Toshinori","family":"Sueyoshi","sequence":"additional","affiliation":[{"name":"Kumamoto University, Kumamoto, Japan"}]}],"member":"320","published-online":{"date-parts":[[2011,12,19]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1145\/1508128.1508150"},{"unstructured":"P. Baneriee Parallel Algorithms for VLSI Computer-aided Design Prentice Hall Int'l Editions New Jersey 1994.   P. Baneriee Parallel Algorithms for VLSI Computer-aided Design Prentice Hall Int'l Editions New Jersey 1994.","key":"e_1_2_1_2_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1145\/329166.329201"},{"unstructured":"H. Sawada M. Kuga M. Amagasaki M. Iida and T. Sueyoshi \"Parappelization of the channel width search for FPGA routing \" Proc. Second Int'l Workshop on Highly-Efficient Accelerators and Reconfiguarable Technologies (HEART2011) pp. 111-116 June 2011.  H. Sawada M. Kuga M. Amagasaki M. Iida and T. Sueyoshi \"Parappelization of the channel width search for FPGA routing \" Proc. Second Int'l Workshop on Highly-Efficient Accelerators and Reconfiguarable Technologies (HEART2011) pp. 111-116 June 2011.","key":"e_1_2_1_4_1"},{"volume-title":"Microelectronics Center of North Carolina (MCNC)","year":"1991","author":"Yang S.","key":"e_1_2_1_5_1"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2082156.2082177","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2082156.2082177","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:06:42Z","timestamp":1750241202000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2082156.2082177"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12,19]]},"references-count":5,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2011,12,19]]}},"alternative-id":["10.1145\/2082156.2082177"],"URL":"https:\/\/doi.org\/10.1145\/2082156.2082177","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2011,12,19]]},"assertion":[{"value":"2011-12-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}