{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:26:53Z","timestamp":1750307213985,"version":"3.41.0"},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002924","name":"Federaci\u00f3n Espa\u00f1ola de Enfermedades Raras","doi-asserted-by":"publisher","award":["TIN2009-14475-C04-02"],"award-info":[{"award-number":["TIN2009-14475-C04-02"]}],"id":[{"id":"10.13039\/501100002924","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003359","name":"Generalitat Valenciana","doi-asserted-by":"publisher","award":["PROMETEO\/2008\/060"],"award-info":[{"award-number":["PROMETEO\/2008\/060"]}],"id":[{"id":"10.13039\/501100003359","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Fundaci\u00f3n S\u00e9neca","award":["00001\/CS\/2007"],"award-info":[{"award-number":["00001\/CS\/2007"]}]},{"DOI":"10.13039\/501100003176","name":"Ministerio de Educaci\u00f3n, Cultura y Deporte","doi-asserted-by":"publisher","award":["AP2008-04387","Consolider Ingenio-2010 CSD2006-00046"],"award-info":[{"award-number":["AP2008-04387","Consolider Ingenio-2010 CSD2006-00046"]}],"id":[{"id":"10.13039\/501100003176","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2012,1]]},"abstract":"<jats:p>Many-core tiled CMP proposals often assume a partially shared last level cache (LLC) since this provides a good compromise between access latency and cache utilization. In this paper, we propose a novel way to map memory addresses to LLC banks that takes into account the average distance between the banks and the tiles that access them. Contrary to traditional approaches, our mapping does not group the tiles in clusters within which all the cores access the same bank for the same addresses. Instead, two neighboring cores access different sets of banks minimizing the average distance travelled by the cache requests. Results for a 64-core CMP show that our proposal improves both execution time and the energy consumed by the network by 13% when compared to a traditional mapping. Moreover, our proposal comes at a negligible cost in terms of hardware and its benefits in both energy and execution time increase with the number of cores.<\/jats:p>","DOI":"10.1145\/2086696.2086704","type":"journal-article","created":{"date-parts":[[2012,1,24]],"date-time":"2012-01-24T16:47:14Z","timestamp":1327423634000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["DAPSCO"],"prefix":"10.1145","volume":"8","author":[{"given":"Antonio","family":"Garc\u00eda-Guirado","sequence":"first","affiliation":[{"name":"Universidad de Murcia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ricardo","family":"Fern\u00e1ndez-Pascual","sequence":"additional","affiliation":[{"name":"Universidad de Murcia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alberto","family":"Ros","sequence":"additional","affiliation":[{"name":"Universidad de Murcia and Universidad Polit\u00e9cnica de Valencia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 M.","family":"Garc\u00eda","sequence":"additional","affiliation":[{"name":"Universidad de Murcia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,1,26]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"AMD. 2007. AMD Athlon 64 X2 Dual-core processor product data sheet.  AMD. 2007. AMD Athlon 64 X2 Dual-core processor product data sheet."},{"volume-title":"Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS). 33--42","author":"Agarwal N.","key":"e_1_2_1_2_1"},{"key":"e_1_2_1_3_1","unstructured":"Agny R. DeLano E. Kumar M. Nachimuthu M. and Shiveley R. 2010. The Intel Itanium Processor 9300 series. Intel white paper.  Agny R. DeLano E. Kumar M. Nachimuthu M. and Shiveley R. 2010. The Intel Itanium Processor 9300 series. Intel white paper."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.10"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.17"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.31"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.129"},{"volume-title":"Proceedings of the 5th International Workshop on Modeling, Benchmarking and Simulation (in conjunction with ISCA). 53--62","author":"Garc\u00eda-Guirado A.","key":"e_1_2_1_8_1"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542289"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555779"},{"key":"e_1_2_1_11_1","unstructured":"Held J. and Koehl S. 2006. Inside Intel core microarchitecture. Intel white paper.  Held J. and Koehl S. 2006. Inside Intel core microarchitecture. Intel white paper."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.83"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088154"},{"volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE). 423--428","author":"Kahng A. B.","key":"e_1_2_1_14_1"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.38"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10017"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840929"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"volume-title":"Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture (HPCA). 74--84","author":"Nayfeh B. A.","key":"e_1_2_1_21_1"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555801"},{"volume-title":"Proceedings of the 16th International Conference on High Performance Computing (HiPC). 79--88","author":"Ros A.","key":"e_1_2_1_23_1"},{"volume-title":"SPARC SoC. In Proceedings of the IEEE Asian Solid-State Circuits Conference. 22--25","author":"Shah M.","key":"e_1_2_1_24_1"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2086696.2086704","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2086696.2086704","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:06:42Z","timestamp":1750241202000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2086696.2086704"}},"subtitle":["Distance-aware partially shared cache organization"],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":24,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2012,1]]}},"alternative-id":["10.1145\/2086696.2086704"],"URL":"https:\/\/doi.org\/10.1145\/2086696.2086704","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2012,1]]},"assertion":[{"value":"2011-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-01-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}