{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,8]],"date-time":"2026-03-08T00:17:00Z","timestamp":1772929020589,"version":"3.50.1"},"reference-count":37,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2012,1]]},"abstract":"<jats:p>\n            In spite of the fact that floating-point arithmetic is costly in terms of silicon area, the joint design of hardware for floating-point and integer arithmetic is seldom considered. While components like multipliers and adders can potentially be shared, floating-point and integer units in contemporary processors are practically disjoint. This work presents a new architecture which tightly integrates floating-point and integer arithmetic in a single datapath. It is mainly intended for use in low-power embedded digital signal processors and therefore the following design constraints were important: limited use of pipelining for the convenience of the compiler; maintaining compatibility with existing technology; minimal area and power consumption for applicability in embedded systems. The architecture is tailored to digital signal processing by combining\n            <jats:italic>floating-point fused multiply-add<\/jats:italic>\n            and\n            <jats:italic>integer multiply-accumulate<\/jats:italic>\n            . It could be deployed in a multi-core system-on-chip designed to support applications with and without dominance of floating-point calculations.\n          <\/jats:p>\n          <jats:p>The VHDL structural description of this architecture is available for download under BSD license. Besides being configurable at design time, it has been thoroughly checked for IEEE-754 compliance by means of a floating-point test suite originating from the IBM Research Labs. A proof-of-concept has also been implemented using STMicroelectronics 65nm technology. This prototype supports 32-bit signed two's complement integers and 41-bit (8-bit exponent and 32-bit significand) floating-point numbers. Our evaluations show that over 67% energy and 19% area can be saved compared to a reference design in which floating-point and integer arithmetic are implemented separately. The area overhead caused by combining floating-point and integer is less than 5%.<\/jats:p>\n          <jats:p>\n            Implemented in ST's general-purpose CMOS technology, the design can operate at a frequency of 1.35GHz, while 667MHz can be achieved in low-power CMOS. Considering that the entire datapath is partitioned in just three pipeline stages, and the fact that the design is intended for use in the low-power domain, these frequencies are adequate. They are in fact competitive with current technology low-power floating-point units. Post-layout estimates indicate that the required area of a low-power implementation can be as small as 0.04mm\n            <jats:sup>2<\/jats:sup>\n            . Power consumption is on the order of several milliwatts. Strengthened by the fact that clock gating could reduce power consumption even further, we think that a shared floating-point and integer architecture is a good choice for signal processing in low-power embedded systems.\n          <\/jats:p>","DOI":"10.1145\/2086696.2086720","type":"journal-article","created":{"date-parts":[[2012,1,24]],"date-time":"2012-01-24T16:47:14Z","timestamp":1327423634000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Sabrewing"],"prefix":"10.1145","volume":"8","author":[{"given":"Tom M.","family":"Bruintjes","sequence":"first","affiliation":[{"name":"University of Twente"}]},{"given":"Karel H. G.","family":"Walters","sequence":"additional","affiliation":[{"name":"University of Twente"}]},{"given":"Sabih H.","family":"Gerez","sequence":"additional","affiliation":[{"name":"University of Twente"}]},{"given":"Bert","family":"Molenkamp","sequence":"additional","affiliation":[{"name":"University of Twente"}]},{"given":"Gerard J. M.","family":"Smit","sequence":"additional","affiliation":[{"name":"University of Twente"}]}],"member":"320","published-online":{"date-parts":[[2012,1,26]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Analog Devices. 2011. SHARC ADSP-21478\/ADSP-21479 (Rev. 0). Datasheet. http:\/\/www.analog.com\/static\/imported-files\/data_sheets\/ADSP-21478_21479.pdf.  Analog Devices. 2011. SHARC ADSP-21478\/ADSP-21479 (Rev. 0). Datasheet. http:\/\/www.analog.com\/static\/imported-files\/data_sheets\/ADSP-21478_21479.pdf."},{"key":"e_1_2_1_2_1","unstructured":"Bishop D. W. 2011. VHDL-2008 support library. http:\/\/www.vhdl.org\/fphdl.  Bishop D. W. 2011. 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Computer Architecture Fourth Edition: A Quantitative Approach. Morgan Kaufmann Publishers Inc. San Francisco CA Chapter A A2--A77.   Hennessy J. L. and Patterson D. A. 2006. Computer Architecture Fourth Edition: A Quantitative Approach. Morgan Kaufmann Publishers Inc. San Francisco CA Chapter A A2--A77."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2007.5"},{"key":"e_1_2_1_11_1","unstructured":"IBM Haifa Research Lab. 2011. FPgen: A deep-knowledge coverage-driven floating-point test generator. https:\/\/www.research.ibm.com\/haifa\/projects\/verification\/fpgen.  IBM Haifa Research Lab. 2011. FPgen: A deep-knowledge coverage-driven floating-point test generator. https:\/\/www.research.ibm.com\/haifa\/projects\/verification\/fpgen."},{"key":"e_1_2_1_12_1","first-page":"10016","article-title":"IEEE 754-2008, standard for floating-point arithmetic. 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