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Cache replacement designed to preserve temporal locality (e.g., LRU) will allocate cache resources proportional to the miss-rate of each competing thread irrespective of whether the cache space will be utilized [Qureshi and Patt 2006]. This is clearly suboptimal as applications vary dramatically in their use of recently accessed data. We address this problem by partitioning a shared cache such that a global goodness metric is optimized. This paper introduces the Gradient-based Cache Partitioning Algorithm (GPA), whose variants optimize either hitrate, total instructions per cycle (IPC) or a weighted IPC metric designed to enforce Quality of Service (QoS) [Iyer 2004]. In the context of QoS, GPA enables us to obtain the maximum throughput of low-priority threads, while ensuring high performance on high-priority threads. The GPA mechanism is robust, low-cost, integrates easily with existing cache designs and improves the throughput of an in-order 8-core system sharing an 8MB L3 cache by \u223c14%.<\/jats:p>","DOI":"10.1145\/2086696.2086723","type":"journal-article","created":{"date-parts":[[2012,1,24]],"date-time":"2012-01-24T16:47:14Z","timestamp":1327423634000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["The gradient-based cache partitioning algorithm"],"prefix":"10.1145","volume":"8","author":[{"given":"William","family":"Hasenplaugh","sequence":"first","affiliation":[{"name":"Intel, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pritpal S.","family":"Ahuja","sequence":"additional","affiliation":[{"name":"Intel, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aamer","family":"Jaleel","sequence":"additional","affiliation":[{"name":"Intel, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Simon","family":"Steely Jr.","sequence":"additional","affiliation":[{"name":"Intel, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joel","family":"Emer","sequence":"additional","affiliation":[{"name":"Intel, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,1,26]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320119"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/986537.986601"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.17"},{"key":"e_1_2_1_4_1","unstructured":"Chiou D. T. 1999. Extending the reach of microprocessors: column and curious caching. Ph.D. thesis Massachusetts Institute of Technology.   Chiou D. T. 1999. Extending the reach of microprocessors: column and curious caching. Ph.D. thesis Massachusetts Institute of Technology."},{"volume-title":"Proceedings of ISCA 29","author":"Dhodapkar A. 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