{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:25:34Z","timestamp":1750307134512,"version":"3.41.0"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2012,2,1]],"date-time":"2012-02-01T00:00:00Z","timestamp":1328054400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council Taiwan","doi-asserted-by":"publisher","award":["100-2628-E-027-008-MY2 and 100-2220-E-001-001"],"award-info":[{"award-number":["100-2628-E-027-008-MY2 and 100-2220-E-001-001"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Storage"],"published-print":{"date-parts":[[2012,2]]},"abstract":"<jats:p>While solid-state drives are excellent alternatives to hard disks in mobile devices, a number of performance and reliability issues need to be addressed. In this work, we design an efficient flash management scheme for the performance improvement of low-cost MLC flash memory devices. Specifically, we design an efficient flash management scheme for multi-chipped flash memory devices with cache support, and develop a two-level address translation mechanism with an adaptive caching policy. We evaluated the approach on real workloads. The results demonstrate that it can improve the performance of multi-chipped solid-state drives through logical-to-physical mappings and concurrent accesses to flash chips.<\/jats:p>","DOI":"10.1145\/2093139.2093142","type":"journal-article","created":{"date-parts":[[2012,2,22]],"date-time":"2012-02-22T18:42:36Z","timestamp":1329936156000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["A caching-oriented management design for the performance enhancement of solid-state drives"],"prefix":"10.1145","volume":"8","author":[{"given":"Yuan-Hao","family":"Chang","sequence":"first","affiliation":[{"name":"Academia Sinica, Taiwan, Republic of China"}]},{"given":"Cheng-Kang","family":"Hsieh","sequence":"additional","affiliation":[{"name":"Academia Sinica, Taiwan, Republic of China"}]},{"given":"Po-Chun","family":"Huang","sequence":"additional","affiliation":[{"name":"National Taiwan University, Taiwan, Republic of China"}]},{"given":"Pi-Cheng","family":"Hsiu","sequence":"additional","affiliation":[{"name":"Academia Sinica, Taiwan, Republic of China"}]}],"member":"320","published-online":{"date-parts":[[2012,2,24]]},"reference":[{"volume-title":"Proceedings of the USENIX 2008 Annual Technical Conference. USENIX Association","author":"Agrawal N.","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","first-page":"732","article-title":"Wear leveling of static areas in flash memory","volume":"6","author":"Ban A.","year":"2004","journal-title":"US Patent"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/11841036_12"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1243418.1243429"},{"key":"e_1_2_1_5_1","unstructured":"Carrier B. 2005. File System Forensic Analysis. Addison Wesley Professional.   Carrier B. 2005. File System Forensic Analysis. Addison Wesley Professional."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508284.1508270"},{"volume-title":"Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 187--196","author":"Chang L.-P.","key":"e_1_2_1_7_1"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/967900.968076"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278533"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278533"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630130"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.126"},{"volume-title":"Proceedings of the 6th Annual IEEE International Conference on Industrial Informatics","year":"2008","author":"Cho Y. J.","key":"e_1_2_1_13_1"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1529282.1529654"},{"key":"e_1_2_1_15_1","unstructured":"DRAMeXchange 2009. Flash contract price http:\/\/www.dramexchange.com\/. DRAMeXchange.  DRAMeXchange 2009. Flash contract price http:\/\/www.dramexchange.com\/. DRAMeXchange."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508284.1508271"},{"key":"e_1_2_1_17_1","unstructured":"Intel Corporation. 1995. FTL Logger Exchanging Data with FTL Systems. Intel Corporation.  Intel Corporation. 1995. FTL Logger Exchanging Data with FTL Systems. Intel Corporation."},{"key":"e_1_2_1_18_1","unstructured":"Intel Corporation. 1998. Understanding the flash translation layer (FTL) specification http:\/\/developer. intel.com\/. Intel Corporation.  Intel Corporation. 1998. Understanding the flash translation layer (FTL) specification http:\/\/developer. intel.com\/. Intel Corporation."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2006.1649669"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.224"},{"volume-title":"Proceedings of the USENIX Technical Conference. 155--164","author":"Kawaguchi A.","key":"e_1_2_1_21_1"},{"volume-title":"Proceedings of the 6th USENIX Conference on File and Storage Technologies (FAST). 239--252","author":"Kim H.","key":"e_1_2_1_22_1"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICISS.2008.23"},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD).","author":"Kuo T.-W.","key":"e_1_2_1_24_1"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.14"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.96"},{"key":"e_1_2_1_27_1","unstructured":"M-Systems. 1998. Flash-memory Translation Layer for NAND flash (NFTL). M-Systems.  M-Systems. 1998. Flash-memory Translation Layer for NAND flash (NFTL). M-Systems."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1416944.1416949"},{"volume-title":"Proceedings of the IEEE International Symposium on Modeling, Analysis and Simulation of Computers and Telecommunication Systems (MASCOTS). 1--3.","author":"Park S.","key":"e_1_2_1_29_1"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176789"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1363686.1364038"},{"key":"e_1_2_1_32_1","unstructured":"Samsung Electronics. 2005. K9K8G08U0M 1G * 8 Bit NAND flash memory data sheet. Samsung Electronics.  Samsung Electronics. 2005. K9K8G08U0M 1G * 8 Bit NAND flash memory data sheet. Samsung Electronics."},{"key":"e_1_2_1_33_1","unstructured":"Samsung Electronics. 2006. K9GAG08U0M 2G x 8bit NAND flash memory data sheet. Samsung Electronics.  Samsung Electronics. 2006. K9GAG08U0M 2G x 8bit NAND flash memory data sheet. Samsung Electronics."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1134650.1134655"},{"key":"e_1_2_1_35_1","unstructured":"STMicroelectronics. 2005. NAND08Gx3C2A 8Gbit multi-level NAND flash memory. STMicroelectronics.  STMicroelectronics. 2005. NAND08Gx3C2A 8Gbit multi-level NAND flash memory. STMicroelectronics."},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1367829.1367831"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/1136649.1137086"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233624"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISORC.2006.13"},{"volume-title":"Proceedings of the Symposium on the ACM\/IEEE Design, Automation and Test in Europe (DATE).","author":"Wu P.-L.","key":"e_1_2_1_40_1"},{"volume-title":"Proceedings of the 20th IEEE\/11th NASA Goddard Conference on Mass Storage Systems and Technologies (MSS). 146--156","author":"Xin Q.","key":"e_1_2_1_41_1"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2004.1277861"}],"container-title":["ACM Transactions on Storage"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2093139.2093142","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2093139.2093142","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:48:44Z","timestamp":1750240124000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2093139.2093142"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2]]},"references-count":42,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,2]]}},"alternative-id":["10.1145\/2093139.2093142"],"URL":"https:\/\/doi.org\/10.1145\/2093139.2093142","relation":{},"ISSN":["1553-3077","1553-3093"],"issn-type":[{"type":"print","value":"1553-3077"},{"type":"electronic","value":"1553-3093"}],"subject":[],"published":{"date-parts":[[2012,2]]},"assertion":[{"value":"2010-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-02-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}