{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:51:03Z","timestamp":1750308663567,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,1,25]],"date-time":"2012-01-25T00:00:00Z","timestamp":1327449600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["248776"],"award-info":[{"award-number":["248776"]}],"id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,1,25]]},"DOI":"10.1145\/2107763.2107776","type":"proceedings-article","created":{"date-parts":[[2012,1,24]],"date-time":"2012-01-24T16:47:19Z","timestamp":1327423639000},"page":"47-50","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["PRO3D"],"prefix":"10.1145","author":[{"given":"Christian","family":"Fabre","sequence":"first","affiliation":[{"name":"CEA LETI, b\u00e2timent CTL, Z. I. de mayencin, Gi\u00e8res, France"}]},{"given":"Iuliana","family":"Bacivarov","sequence":"additional","affiliation":[{"name":"Computer Engineering and Networks Laboratory, Gloriastrasse, Z\u00fcrich, Switzerland"}]},{"given":"Eth","family":"Z\u00fcrich","sequence":"additional","affiliation":[{"name":"Computer Engineering and Networks Laboratory, Gloriastrasse, Z\u00fcrich, Switzerland"}]},{"given":"Ananda","family":"Basu","sequence":"additional","affiliation":[{"name":"VERIMAG Centre Equation, Gi\u00e8res, France"}]},{"given":"Martino","family":"Ruggiero","sequence":"additional","affiliation":[{"name":"University of Bologna, Viale Risorgimento, Bologna, Italy"}]},{"given":"David","family":"Atienza","sequence":"additional","affiliation":[{"name":"EPFL, ESL, Lausanne, Switzerland"}]},{"given":"\u00c9ric","family":"Flamand","sequence":"additional","affiliation":[{"name":"ST Microelectronics, Grenoble, France"}]}],"member":"320","published-online":{"date-parts":[[2012,1,25]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MS.2011.27"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-005-6648-1"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2011.6089691"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2011.5970506"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/1812707.1812726"},{"key":"e_1_3_2_1_6_1","volume-title":"Embedding Formal Performance Analysis into the Design Cycle of MPSoCs for Real-time Streaming Applications","author":"Huang K.","year":"2011","unstructured":"K. Huang , W. Haid , I. Bacivarov , M. Keller , and L. Thiele . Embedding Formal Performance Analysis into the Design Cycle of MPSoCs for Real-time Streaming Applications . 2011 . K. Huang, W. Haid, I. Bacivarov, M. Keller, and L. Thiele. Embedding Formal Performance Analysis into the Design Cycle of MPSoCs for Real-time Streaming Applications. 2011."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1878921.1878952"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039390"},{"key":"e_1_3_2_1_9_1","unstructured":"PRO3D -- Programming for Future 3D Multicore Architectures 2010. http:\/\/pro3d.eu.  PRO3D -- Programming for Future 3D Multicore Architectures 2010. http:\/\/pro3d.eu."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763104"},{"key":"e_1_3_2_1_11_1","first-page":"169","volume-title":"Int. Symp. on Systems-on-Chip","author":"Ruggiero M.","year":"2004","unstructured":"M. Ruggiero , F. Angiolini , F. Poletti , D. Bertozzi , L. Benini , and R. Zafalon . Scalability analysis of evolving SoC interconnect protocols . In Int. Symp. on Systems-on-Chip , pages 169 -- 172 , 2004 . M. Ruggiero, F. Angiolini, F. Poletti, D. Bertozzi, L. Benini, and R. Zafalon. Scalability analysis of evolving SoC interconnect protocols. In Int. Symp. on Systems-on-Chip, pages 169--172, 2004."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785552"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/2045364.2045393"},{"key":"e_1_3_2_1_14_1","first-page":"1","volume-title":"Thermal Investigations of ICs and Systems (THERMINIC), 2010 16th International Workshop on","author":"Sridhar A.","year":"2010","unstructured":"A. Sridhar , A. Vincenzi , M. Ruggiero , T. Brunschwiler , and D. Atienza . Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries . In Thermal Investigations of ICs and Systems (THERMINIC), 2010 16th International Workshop on , pages 1 -- 6 , 2010 . A. Sridhar, A. Vincenzi, M. Ruggiero, T. Brunschwiler, and D. Atienza. Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries. In Thermal Investigations of ICs and Systems (THERMINIC), 2010 16th International Workshop on, pages 1--6, 2010."},{"key":"e_1_3_2_1_15_1","volume-title":"Nov.","author":"STM","year":"2010","unstructured":"STM and CEA. Platform 2012: A Manycore Programmable Accelerator for Ultra-Efficient Embedded Computing in Nanometer Technology , Nov. 2010 . Whitepaper . STM and CEA. Platform 2012: A Manycore Programmable Accelerator for Ultra-Efficient Embedded Computing in Nanometer Technology, Nov. 2010. Whitepaper."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2007.53"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/2016802.2016842"}],"event":{"name":"INA-OCMC '12: On-Chip, Multi-Chip","acronym":"INA-OCMC '12","location":"Paris France"},"container-title":["Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2107763.2107776","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2107763.2107776","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:00:26Z","timestamp":1750276826000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2107763.2107776"}},"subtitle":["programming for future 3D manycore architectures"],"short-title":[],"issued":{"date-parts":[[2012,1,25]]},"references-count":17,"alternative-id":["10.1145\/2107763.2107776","10.1145\/2107763"],"URL":"https:\/\/doi.org\/10.1145\/2107763.2107776","relation":{},"subject":[],"published":{"date-parts":[[2012,1,25]]},"assertion":[{"value":"2012-01-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}