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For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30% better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput\/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board).<\/jats:p>","DOI":"10.1145\/2133352.2133354","type":"journal-article","created":{"date-parts":[[2012,3,20]],"date-time":"2012-03-20T12:04:05Z","timestamp":1332245045000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["On the exploitation of a high-throughput SHA-256 FPGA design for HMAC"],"prefix":"10.1145","volume":"5","author":[{"given":"Harris E.","family":"Michail","sequence":"first","affiliation":[{"name":"University of Patras, Patras, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George S.","family":"Athanasiou","sequence":"additional","affiliation":[{"name":"University of Patras, Patras, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vasilis","family":"Kelefouras","sequence":"additional","affiliation":[{"name":"University of Patras, Patras, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George","family":"Theodoridis","sequence":"additional","affiliation":[{"name":"University of Patras, Patras, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Costas E.","family":"Goutis","sequence":"additional","affiliation":[{"name":"University of Patras, Patras, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,3,23]]},"reference":[{"unstructured":"CAST Inc. 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The status of MD5 after a recent attack . RSALabs' CryptoBytes. 2 , 2 . Dobbertin, H. 1996. The status of MD5 after a recent attack. RSALabs' CryptoBytes. 2, 2.","journal-title":"RSALabs' CryptoBytes."},{"doi-asserted-by":"publisher","key":"e_1_2_1_6_1","DOI":"10.1109\/ICECS.2002.1046454"},{"unstructured":"Doraswamy N. and Harkins D. 2003. IPSec\u2014The New Security Standard for the Internet Intranets and Virtual Private Networks. 2nd Ed. Prentice-Hall PTR Publications.   Doraswamy N. and Harkins D. 2003. IPSec\u2014The New Security Standard for the Internet Intranets and Virtual Private Networks. 2nd Ed. Prentice-Hall PTR Publications.","key":"e_1_2_1_7_1"},{"unstructured":"Friedl S. 2003. An illustrated guide to IPSec. http:\/\/www.unixwiz.netltechtips\/iguide-ipsec.html.  Friedl S. 2003. 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Hodjat, A. and Verbauwhede, L. 2004. A 21.54 Gbits\/s fully pipelined AES processor on FPGA. In Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE Computer Society, Los Alamitos, CA, 308--309.","key":"e_1_2_1_12_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_13_1","DOI":"10.1109\/MSP.2004.20"},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1109\/ITICT.2005.1609672"},{"volume-title":"Proceedings of the 4th International Conference on Autonomic and Trusted Computing (ATC'07)","author":"Kim M.","unstructured":"Kim , M. , Kim , Y. , Ryou , J. , and Jun , S . 2007. Efficient implementation of the keyed-hash message authentication code based on SHA-1 algorithm for mobile trusted computing . In Proceedings of the 4th International Conference on Autonomic and Trusted Computing (ATC'07) . 410--419. Kim, M., Kim, Y., Ryou, J., and Jun, S. 2007. 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Architectural design features of a programmable high throughput reconfigurable SHA-2 Processor. J. Inf. Assur. Secur. 2, 147--158.","journal-title":"J. Inf. Assur. Secur."}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2133352.2133354","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2133352.2133354","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:06:05Z","timestamp":1750241165000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2133352.2133354"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":40,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,3]]}},"alternative-id":["10.1145\/2133352.2133354"],"URL":"https:\/\/doi.org\/10.1145\/2133352.2133354","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2012,3]]},"assertion":[{"value":"2011-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-03-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}