{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,27]],"date-time":"2025-09-27T14:01:24Z","timestamp":1758981684134,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,2,22]],"date-time":"2012-02-22T00:00:00Z","timestamp":1329868800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,2,22]]},"DOI":"10.1145\/2145694.2145738","type":"proceedings-article","created":{"date-parts":[[2012,2,22]],"date-time":"2012-02-22T18:42:35Z","timestamp":1329936155000},"page":"255-264","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Reducing the cost of floating-point mantissa alignment and normalization in FPGAs"],"prefix":"10.1145","author":[{"given":"Yehdhih Ould Mohammed","family":"Moctar","sequence":"first","affiliation":[{"name":"University of California, Riverside, Riverside, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nithin","family":"George","sequence":"additional","affiliation":[{"name":"Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hadi","family":"Parandeh-Afshar","sequence":"additional","affiliation":[{"name":"Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Ienne","sequence":"additional","affiliation":[{"name":"Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guy G.F.","family":"Lemieux","sequence":"additional","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philip","family":"Brisk","sequence":"additional","affiliation":[{"name":"University of California, Riverside, Riverside, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2012,2,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.912041"},{"key":"e_1_3_2_1_3_1","volume-title":"A system for sequential synthesis and verification","author":"Berkeley Logic Synthesis and Verification Group","year":"2005","unstructured":"Berkeley Logic Synthesis and Verification Group . \"ABC : A system for sequential synthesis and verification .: December 2005 release. URL = http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc Berkeley Logic Synthesis and Verification Group. \"ABC: A system for sequential synthesis and verification.: December 2005 release. URL= http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329203"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508155"},{"key":"e_1_3_2_1_6_1","volume-title":"Conf. Field Programmable Logic and Applications (FPL '09)","author":"de Dinechin F.","year":"2009","unstructured":"de Dinechin , F. , Klein , C. , and Pasca , B ., \" Generating high-performance custom floating-point pipelines,\" Int . Conf. Field Programmable Logic and Applications (FPL '09) , Aug. 31 - Sept. 2, 2009 . DOI=http:\/\/dx.doi.org\/10.1109\/FPL.2009.527255\/ 10.1109\/FPL.2009.527255 de Dinechin, F., Klein, C., and Pasca, B., \"Generating high-performance custom floating-point pipelines,\" Int. Conf. Field Programmable Logic and Applications (FPL '09), Aug. 31-Sept. 2, 2009. DOI=http:\/\/dx.doi.org\/10.1109\/FPL.2009.527255\/"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1331897.1331902"},{"key":"e_1_3_2_1_8_1","first-page":"1","article-title":"Implementing barrel shifters using multipliers","author":"Gigliotti P.","year":"2004","unstructured":"Gigliotti , P. , \" Implementing barrel shifters using multipliers ,\" XAPP -- Application Note: Virtex II Family , pp. 1 -- 4 , Aug. , 2004 . URL= http:\/\/www.xilinx.com\/support\/documentation\/application_notes\/xapp195.pdf Gigliotti, P., \"Implementing barrel shifters using multipliers,\" XAPP -- Application Note: Virtex II Family, pp. 1--4, Aug., 2004. URL= http:\/\/www.xilinx.com\/support\/documentation\/application_notes\/xapp195.pdf","journal-title":"XAPP -- Application Note: Virtex II Family"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2006616"},{"key":"e_1_3_2_1_10_1","unstructured":"IWLS 2005 benchmarks. URL= http:\/\/iwls.org\/iwls2005\/benchmarks.html  IWLS 2005 benchmarks. URL= http:\/\/iwls.org\/iwls2005\/benchmarks.html"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2026651"},{"key":"e_1_3_2_1_12_1","first-page":"323","volume-title":"IEEE Northeast Workshop on Circuits & Systems (IEEE-NEWCAS '05)","author":"Jamieson P.","year":"2005","unstructured":"Jamieson , P. , and Rose , J ., \" Mapping multiplexers onto hard multipliers in FPGAs,\" 3rd Int . IEEE Northeast Workshop on Circuits & Systems (IEEE-NEWCAS '05) , pp. 323 -- 326 , June 19-22, 2005 . DOI= http:\/\/dx.doi.org\/10.1109\/NEWCAS.2005.1496692 10.1109\/NEWCAS.2005.1496692 Jamieson, P., and Rose, J., \"Mapping multiplexers onto hard multipliers in FPGAs,\" 3rd Int. IEEE Northeast Workshop on Circuits & Systems (IEEE-NEWCAS '05), pp. 323--326, June 19-22, 2005. DOI= http:\/\/dx.doi.org\/10.1109\/NEWCAS.2005.1496692"},{"key":"e_1_3_2_1_13_1","volume-title":"Apr. 29","author":"Kaviani A.","year":"2003","unstructured":"Kaviani , A. , FPGA with improved structure for implementing large multiplexors. U.S. patent, no. US 6,556,042 B1 , Apr. 29 , 2003 . Kaviani, A., FPGA with improved structure for implementing large multiplexors. U.S. patent, no. US 6,556,042 B1, Apr. 29, 2003."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344695"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391671"},{"key":"e_1_3_2_1_16_1","first-page":"355","volume-title":"Conf. Field Programmable Logic and Applications, (FPL '08)","author":"Langhammer M.","year":"2008","unstructured":"Langhammer , M. , \" Floating point datapath synthesis for FPGAs,\" Int . Conf. Field Programmable Logic and Applications, (FPL '08) , pp. 355 -- 360 , Sept. 8 --10 , 2008 . DOI= http:\/\/dx.doi.org\/10.1109\/FPL.2008.4629963 10.1109\/FPL.2008.4629963 Langhammer, M., \"Floating point datapath synthesis for FPGAs,\" Int. Conf. Field Programmable Logic and Applications, (FPL '08), pp.355--360, Sept. 8--10, 2008. DOI= http:\/\/dx.doi.org\/10.1109\/FPL.2008.4629963"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2009.54"},{"key":"e_1_3_2_1_18_1","first-page":"41","volume-title":"Directional and single-driver wires in FPGA interconnect,\" IEEE International Conference on Field-Programmable Technology (FPT '04)","author":"Lemieux G.","year":"2004","unstructured":"Lemieux , G. Lee , E. Tom , M. , and Yu , A . \" Directional and single-driver wires in FPGA interconnect,\" IEEE International Conference on Field-Programmable Technology (FPT '04) , pp. 41 -- 48 , Dec. 6-8, 2004 , DOI: http:\/\/dx.doi.org\/10.1109\/FPT.2004.1393249 10.1109\/FPT.2004.1393249 Lemieux, G. Lee, E. Tom, M., and Yu, A. \"Directional and single-driver wires in FPGA interconnect,\" IEEE International Conference on Field-Programmable Technology (FPT '04), pp. 41--48, Dec. 6-8, 2004, DOI: http:\/\/dx.doi.org\/10.1109\/FPT.2004.1393249"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360299"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329208"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065692"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.15"},{"key":"e_1_3_2_1_26_1","volume-title":"September 16","author":"Xilinx Corporation","year":"2009","unstructured":"Xilinx Corporation . Virtex-6 FPGA DSP48E1 Slice User Guide UG369 (v1.2) , September 16 , 2009 . URL = http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug369.pdf Xilinx Corporation. Virtex-6 FPGA DSP48E1 Slice User Guide UG369 (v1.2), September 16, 2009. URL= http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug369.pdf"}],"event":{"name":"FPGA '12: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA '12"},"container-title":["Proceedings of the ACM\/SIGDA international symposium on Field Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2145694.2145738","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2145694.2145738","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T09:54:51Z","timestamp":1750240491000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2145694.2145738"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2,22]]},"references-count":26,"alternative-id":["10.1145\/2145694.2145738","10.1145\/2145694"],"URL":"https:\/\/doi.org\/10.1145\/2145694.2145738","relation":{},"subject":[],"published":{"date-parts":[[2012,2,22]]},"assertion":[{"value":"2012-02-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}