{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:50:32Z","timestamp":1750308632876,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":44,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,12,3]],"date-time":"2011-12-03T00:00:00Z","timestamp":1322870400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,12,3]]},"DOI":"10.1145\/2155620.2155651","type":"proceedings-article","created":{"date-parts":[[2012,3,6]],"date-time":"2012-03-06T13:18:26Z","timestamp":1331039906000},"page":"260-271","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":22,"title":["System-level integrated server architectures for scale-out datacenters"],"prefix":"10.1145","author":[{"given":"Sheng","family":"Li","sequence":"first","affiliation":[{"name":"Hewlett-Packard Labs"}]},{"given":"Kevin","family":"Lim","sequence":"additional","affiliation":[{"name":"Hewlett-Packard Labs"}]},{"given":"Paolo","family":"Faraboschi","sequence":"additional","affiliation":[{"name":"Hewlett-Packard Labs"}]},{"given":"Jichuan","family":"Chang","sequence":"additional","affiliation":[{"name":"Hewlett-Packard Labs"}]},{"given":"Parthasarathy","family":"Ranganathan","sequence":"additional","affiliation":[{"name":"Hewlett-Packard Labs"}]},{"given":"Norman P.","family":"Jouppi","sequence":"additional","affiliation":[{"name":"Hewlett-Packard Labs"}]}],"member":"320","published-online":{"date-parts":[[2011,12,3]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"http:\/\/www.calxeda.com\/.  http:\/\/www.calxeda.com\/."},{"key":"e_1_3_2_1_2_1","unstructured":"http:\/\/www.seamicro.com\/.  http:\/\/www.seamicro.com\/."},{"key":"e_1_3_2_1_3_1","unstructured":"http:\/\/www.eurocloudserver.com\/.  http:\/\/www.eurocloudserver.com\/."},{"key":"e_1_3_2_1_4_1","unstructured":"http:\/\/www.dell.com\/.  http:\/\/www.dell.com\/."},{"key":"e_1_3_2_1_5_1","unstructured":"http:\/\/www.hp.com\/.  http:\/\/www.hp.com\/."},{"key":"e_1_3_2_1_7_1","unstructured":"AMD \"AMD Opteron Processor Benchmarking for Clustered Systems \" AMD WhitePaper 2003.  AMD \"AMD Opteron Processor Benchmarking for Clustered Systems \" AMD WhitePaper 2003."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629577"},{"key":"e_1_3_2_1_9_1","unstructured":"ARM http:\/\/www.arm.com\/products\/processors\/cortex-a\/cortex-a9.php.  ARM http:\/\/www.arm.com\/products\/processors\/cortex-a\/cortex-a9.php."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"e_1_3_2_1_11_1","unstructured":"M. Bohr \"Silicon Technology for 32 nm and Beyond System-on-Chip Products \" in IDF'09 2009.  M. Bohr \"Silicon Technology for 32 nm and Beyond System-on-Chip Products \" in IDF'09 2009."},{"key":"e_1_3_2_1_13_1","unstructured":"Cadence InCyte Chip Estimator \"http:\/\/www.chipestimate.com\/.\"  Cadence InCyte Chip Estimator \"http:\/\/www.chipestimate.com\/.\""},{"key":"e_1_3_2_1_14_1","unstructured":"B. Carlso \"Going Beyond a Faster Horse to Transform Mobile Devices \" Texas Instruments Tech. Rep. May 2011.  B. Carlso \"Going Beyond a Faster Horse to Transform Mobile Devices \" Texas Instruments Tech. Rep. May 2011."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508270"},{"key":"e_1_3_2_1_17_1","first-page":"368","volume-title":"A 12.3mW 12.5Gb\/s complete transceiver in 65nm CMOS,\" in ISSCC'10","author":"Fukuda K.","year":"2010","unstructured":"K. Fukuda , , \" A 12.3mW 12.5Gb\/s complete transceiver in 65nm CMOS,\" in ISSCC'10 , 2010 , pp. 368 -- 369 . K. Fukuda, et al., \"A 12.3mW 12.5Gb\/s complete transceiver in 65nm CMOS,\" in ISSCC'10, 2010, pp. 368--369."},{"key":"e_1_3_2_1_18_1","unstructured":"J. Hamilton \"Overall Data Center Costs \" http:\/\/perspectives.mvdirona.com\/2010\/09\/18\/OverallDataCenterCosts.aspx.  J. Hamilton \"Overall Data Center Costs \" http:\/\/perspectives.mvdirona.com\/2010\/09\/18\/OverallDataCenterCosts.aspx."},{"key":"e_1_3_2_1_19_1","first-page":"436","volume-title":"ISSCC'07","author":"Harwood M.","year":"2007","unstructured":"M. Harwood , A 12.5Gb\/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery,\" in ISSCC'07 , 2007 , pp. 436 -- 591 . M. Harwood, et al., \"A 12.5Gb\/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery,\" in ISSCC'07, 2007, pp. 436--591."},{"key":"e_1_3_2_1_20_1","volume-title":"The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines","author":"Hoelzle U.","year":"2009","unstructured":"U. Hoelzle and L. A. Barroso , The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines , 1 st ed. Morgan and Claypool Publishers , 2009 . U. Hoelzle and L. A. Barroso, The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines, 1st ed. Morgan and Claypool Publishers, 2009.","edition":"1"},{"key":"e_1_3_2_1_21_1","volume-title":"Rep.","author":"Class HP","year":"2009","unstructured":"HP, \" HP BladeSystem c- Class SAN connectivity technology brief,\" Tech . Rep. , 2009 . HP, \"HP BladeSystem c-Class SAN connectivity technology brief,\" Tech. Rep., 2009."},{"key":"e_1_3_2_1_22_1","unstructured":"Intel http:\/\/www.intel.com\/products\/processor\/atom\/techdocs.htms.  Intel http:\/\/www.intel.com\/products\/processor\/atom\/techdocs.htms."},{"volume-title":"Rep.","year":"2009","key":"e_1_3_2_1_23_1","unstructured":"Intel, \"An Introduction to the Intel QuickPath Interconnect,\" Tech . Rep. , 2009 . Intel, \"An Introduction to the Intel QuickPath Interconnect,\" Tech. Rep., 2009."},{"key":"e_1_3_2_1_24_1","unstructured":"JEDEC Solid State Technology Association \"http:\/\/www.jedec.org\/.\"  JEDEC Solid State Technology Association \"http:\/\/www.jedec.org\/.\""},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1231996.1232000"},{"key":"e_1_3_2_1_26_1","volume-title":"ISSCC'10","author":"Jotwani R.","year":"2010","unstructured":"R. Jotwani , \"An x86-64 Core Implemented in 32nm SOI CMOS,\" in ISSCC'10 , 2010 . R. Jotwani, \"An x86-64 Core Implemented in 32nm SOI CMOS,\" in ISSCC'10, 2010."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","DOI":"10.1017\/CBO9780511805172","volume-title":"Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication","author":"Kaeslin H.","year":"2008","unstructured":"H. Kaeslin , Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication , 1 st ed. Cambridge University Press , April 2008 . H. Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, 1st ed. Cambridge University Press, April 2008.","edition":"1"},{"key":"e_1_3_2_1_28_1","unstructured":"Kaeslin Hubert \"ASIC Cost Estimator webpage at http:\/\/www.dz.ee.ethz.ch\/?id=1592.\"  Kaeslin Hubert \"ASIC Cost Estimator webpage at http:\/\/www.dz.ee.ethz.ch\/?id=1592.\""},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/622212.623216"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168873"},{"key":"e_1_3_2_1_31_1","first-page":"58","article-title":"A family of 45nm IA processors","author":"Kumar R.","year":"2009","unstructured":"R. Kumar and G. Hinton , \" A family of 45nm IA processors ,\" ISSCC , pp. 58 -- 59 , 2009 . R. Kumar and G. Hinton, \"A family of 45nm IA processors,\" ISSCC, pp. 58--59, 2009.","journal-title":"ISSCC"},{"key":"e_1_3_2_1_32_1","unstructured":"T. Lanier \"Exploring the Design of the Cortex-A15 Processor \" ARM Tech. Rep.  T. Lanier \"Exploring the Design of the Cortex-A15 Processor \" ARM Tech. Rep."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_34_1","volume-title":"CACTI-P: Architecture-Level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques,\" in ICCAD","author":"Li S.","year":"2011","unstructured":"S. Li , K. Chen , J. H. Ahn , J. B. Brockman , and N. P. Jouppi , \" CACTI-P: Architecture-Level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques,\" in ICCAD , 2011 . S. Li, K. Chen, J. H. Ahn, J. B. Brockman, and N. P. Jouppi, \"CACTI-P: Architecture-Level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques,\" in ICCAD, 2011."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.37"},{"key":"e_1_3_2_1_36_1","unstructured":"The Wall Street Journal 2010 Marvell Unveils 1.6GHz Quad-Core ARMADA XP Platform for Enterprise Class Cloud Computing Applications"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771772"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.61"},{"key":"e_1_3_2_1_39_1","first-page":"440","volume-title":"ISSCC'07","author":"Palmer R.","year":"2007","unstructured":"R. Palmer , A 14mW 6.25Gb\/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications,\" in ISSCC'07 , 2007 , pp. 440 -- 614 . R. Palmer, et al., \"A 14mW 6.25Gb\/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications,\" in ISSCC'07, 2007, pp. 440--614."},{"key":"e_1_3_2_1_40_1","unstructured":"PCI Special Interest Group \"http:\/\/www.pcisig.com\/.\"  PCI Special Interest Group \"http:\/\/www.pcisig.com\/.\""},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508293.1508303"},{"key":"e_1_3_2_1_42_1","first-page":"62","volume-title":"Active storage for large-scale data mining and multimedia,\" in VLDB '98","author":"Riedel E.","year":"1998","unstructured":"E. Riedel , G. A. Gibson , and C. Faloutsos , \" Active storage for large-scale data mining and multimedia,\" in VLDB '98 , 1998 , pp. 62 -- 73 . E. Riedel, G. A. Gibson, and C. Faloutsos, \"Active storage for large-scale data mining and multimedia,\" in VLDB '98, 1998, pp. 62--73."},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885041"},{"key":"e_1_3_2_1_44_1","unstructured":"Semiconductor Industries Association \"International Technology Roadmap for Semiconductors.\/Model for Assessment of CMOS Technologies and Roadmaps (MASTAR) http:\/\/www.itrs.net\/.\"  Semiconductor Industries Association \"International Technology Roadmap for Semiconductors.\/Model for Assessment of CMOS Technologies and Roadmaps (MASTAR) http:\/\/www.itrs.net\/.\""},{"key":"e_1_3_2_1_45_1","unstructured":"Serial ATA International Organization \"http:\/\/www.sata-io.org\/.\"  Serial ATA International Organization \"http:\/\/www.sata-io.org\/.\""},{"key":"e_1_3_2_1_46_1","first-page":"98","volume-title":"ISSCC'10","author":"Shin J.","year":"2010","unstructured":"J. Shin , A 40nm 16-Core 128-Thread CMT SPARC SoC Processor ,\" in ISSCC'10 , 2010 , pp. 98 -- 99 . J. Shin, et al., \"A 40nm 16-Core 128-Thread CMT SPARC SoC Processor,\" in ISSCC'10, 2010, pp. 98--99."},{"key":"e_1_3_2_1_47_1","first-page":"264","article-title":"A Fully Integrated Multi-CPU, GPU and Memory Controller 32nm Processor","author":"Yuffe M.","year":"2011","unstructured":"M. Yuffe , E. Knoll , M. Mehalel , J. Shor , and T. Kurts , \" A Fully Integrated Multi-CPU, GPU and Memory Controller 32nm Processor ,\" in ISSCC , Feb. 2011 , pp. 264 -- 266 . M. Yuffe, E. Knoll, M. Mehalel, J. Shor, and T. Kurts, \"A Fully Integrated Multi-CPU, GPU and Memory Controller 32nm Processor,\" in ISSCC, Feb. 2011, pp. 264--266.","journal-title":"ISSCC"}],"event":{"name":"MICRO-44: The 44th Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["IEEE","ACM Association for Computing Machinery","UFRGS Universidade Federal do Rio Grande do Sul","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS Computer Society"],"location":"Porto Alegre Brazil","acronym":"MICRO-44"},"container-title":["Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2155620.2155651","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2155620.2155651","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:07:59Z","timestamp":1750273679000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2155620.2155651"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12,3]]},"references-count":44,"alternative-id":["10.1145\/2155620.2155651","10.1145\/2155620"],"URL":"https:\/\/doi.org\/10.1145\/2155620.2155651","relation":{},"subject":[],"published":{"date-parts":[[2011,12,3]]},"assertion":[{"value":"2011-12-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}