{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,17]],"date-time":"2026-07-17T15:55:19Z","timestamp":1784303719293,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":58,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,12,3]],"date-time":"2011-12-03T00:00:00Z","timestamp":1322870400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,12,3]]},"DOI":"10.1145\/2155620.2155655","type":"proceedings-article","created":{"date-parts":[[2012,3,6]],"date-time":"2012-03-06T13:18:26Z","timestamp":1331039906000},"page":"296-307","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":74,"title":["Hardware transactional memory for GPU architectures"],"prefix":"10.1145","author":[{"given":"Wilson W. L.","family":"Fung","sequence":"first","affiliation":[{"name":"University of British Columbia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Inderpreet","family":"Singh","sequence":"additional","affiliation":[{"name":"University of British Columbia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrew","family":"Brownsword","sequence":"additional","affiliation":[{"name":"University of British Columbia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tor M.","family":"Aamodt","sequence":"additional","affiliation":[{"name":"University of British Columbia"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2011,12,3]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"NVIDIA Forums - atomicCAS does NOT seem to work. http:\/\/forums.nvidia.com\/index.php?showtopic=98444.  NVIDIA Forums - atomicCAS does NOT seem to work. http:\/\/forums.nvidia.com\/index.php?showtopic=98444."},{"key":"e_1_3_2_1_2_1","volume-title":"Advances in Knowledge Discovery and Data Mining","author":"Agrawal R.","year":"1996","unstructured":"R. Agrawal Advances in Knowledge Discovery and Data Mining . chapter Fast Discovery of Association Rules. American Association for Artificial Intelligence , 1996 . R. Agrawal et al. Advances in Knowledge Discovery and Data Mining. chapter Fast Discovery of Association Rules. American Association for Artificial Intelligence, 1996."},{"key":"e_1_3_2_1_3_1","volume-title":"March","author":"AMD.","year":"2009","unstructured":"AMD. R700-Family Instruction Set Architecture , March 2009 . AMD. R700-Family Instruction Set Architecture, March 2009."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2007.370254"},{"key":"e_1_3_2_1_5_1","volume-title":"IBM's new transactional memory: make-or-break time for multithreaded revolution","year":"2011","unstructured":"Ars Technica. IBM's new transactional memory: make-or-break time for multithreaded revolution , 2011 . Ars Technica. IBM's new transactional memory: make-or-break time for multithreaded revolution, 2011."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_3_2_1_7_1","author":"Blake G.","year":"2011","unstructured":"G. Blake , R. G. Dreslinski , and T. Mudge . Bloom Filter Guided Transaction Scheduling. In HPCA , 2011 . G. Blake, R. G. Dreslinski, and T. Mudge. Bloom Filter Guided Transaction Scheduling. In HPCA, 2011.","journal-title":"Bloom Filter Guided Transaction Scheduling. In HPCA"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250667"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250674"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.24"},{"key":"e_1_3_2_1_11_1","volume-title":"Cloth in OpenCL","author":"Brownsword A.","year":"2009","unstructured":"A. Brownsword . Cloth in OpenCL , 2009 . A. Brownsword. Cloth in OpenCL, 2009."},{"key":"e_1_3_2_1_12_1","volume-title":"GPU Computing Gems Emerald Edition","author":"Burtscher M.","year":"2011","unstructured":"M. Burtscher and K. Pingali . An Efficient CUDA Implementation of the Tree-based Barnes Hut n-Body Algorithm . Chapter 6 in GPU Computing Gems Emerald Edition , 2011 . M. Burtscher and K. Pingali. An Efficient CUDA Implementation of the Tree-based Barnes Hut n-Body Algorithm. Chapter 6 in GPU Computing Gems Emerald Edition, 2011."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950372"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/2386208.2386228"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.13"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346189"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.40"},{"key":"e_1_3_2_1_18_1","volume-title":"United States Patent #7,353,369: System and Method for Managing Divergent Threads in a SIMD Architecture","author":"Coon B. W.","year":"2008","unstructured":"B. W. Coon United States Patent #7,353,369: System and Method for Managing Divergent Threads in a SIMD Architecture ( Assignee NVIDIA Corp .), April 2008 . B. W. Coon et al. United States Patent #7,353,369: System and Method for Managing Divergent Threads in a SIMD Architecture (Assignee NVIDIA Corp.), April 2008."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1693453.1693464"},{"key":"e_1_3_2_1_20_1","volume-title":"Morgan Kaufmann","author":"Dally W. J.","year":"2004","unstructured":"W. J. Dally and B. Towles . Interconnection Networks . Morgan Kaufmann , 2004 . W. J. Dally and B. Towles. Interconnection Networks. Morgan Kaufmann, 2004."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508263"},{"key":"e_1_3_2_1_22_1","volume-title":"HPCA","author":"Ferdman M.","year":"2011","unstructured":"M. Ferdman : A Scalable Directory for Many-Core Systems . In HPCA , 2011 . M. Ferdman et al. Cuckoo Directory: A Scalable Directory for Many-Core Systems. In HPCA, 2011."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.12"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1543753.1543756"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1772954.1772970"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1345206.1345233"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01728-5","author":"Harris T.","year":"2010","unstructured":"T. Harris , J. Larus , and R. Rajwar . Transactional Memory. 2010 . T. Harris, J. Larus, and R. Rajwar. Transactional Memory. 2010.","journal-title":"Transactional Memory."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854291"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1958746.1958795"},{"key":"e_1_3_2_1_31_1","unstructured":"Khronos Group. OpenCL. http:\/\/www.khronos.org\/opencl\/.  Khronos Group. OpenCL. http:\/\/www.khronos.org\/opencl\/."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1007\/11919568_59"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2006.180"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/800031.808581"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250673"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/133994.134067"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1365490.1365500"},{"key":"e_1_3_2_1_40_1","volume-title":"October","author":"NVIDIA.","year":"2009","unstructured":"NVIDIA. NVIDIA's Next Generation CUDA Compute Architecture: Fermi , October 2009 . NVIDIA. NVIDIA's Next Generation CUDA Compute Architecture: Fermi, October 2009."},{"key":"e_1_3_2_1_41_1","volume-title":"NVIDIA CUDA Programming Guide v3.1","author":"NVIDIA Corp.","year":"2010","unstructured":"NVIDIA Corp. NVIDIA CUDA Programming Guide v3.1 , 2010 . NVIDIA Corp. NVIDIA CUDA Programming Guide v3.1, 2010."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299063"},{"key":"e_1_3_2_1_43_1","volume-title":"Towards Scalar Synchronization in SIMT Architectures. Master's thesis","author":"Ramamurthy A.","year":"2011","unstructured":"A. Ramamurthy . Towards Scalar Synchronization in SIMT Architectures. Master's thesis , University of British Columbia , 2011 . A. Ramamurthy. Towards Scalar Synchronization in SIMT Architectures. Master's thesis, University of British Columbia, 2011."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.9"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.5555\/1331699.1331713"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/1399504.1360617"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.17"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378583"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995904"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.54"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669132"},{"key":"e_1_3_2_1_53_1","volume-title":"CudaCuts: Fast Graph Cuts on the GPU. In CVPRW '08","author":"Vineet V.","year":"2008","unstructured":"V. Vineet and P. Narayanan . CudaCuts: Fast Graph Cuts on the GPU. In CVPRW '08 , 2008 . V. Vineet and P. Narayanan. CudaCuts: Fast Graph Cuts on the GPU. In CVPRW '08, 2008."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/800224.806813"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452013"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346204"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378564"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854294"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854311"}],"event":{"name":"MICRO-44: The 44th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Porto Alegre Brazil","acronym":"MICRO-44","sponsor":["IEEE","ACM Association for Computing Machinery","UFRGS Universidade Federal do Rio Grande do Sul","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS Computer Society"]},"container-title":["Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2155620.2155655","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2155620.2155655","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:07:59Z","timestamp":1750273679000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2155620.2155655"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12,3]]},"references-count":58,"alternative-id":["10.1145\/2155620.2155655","10.1145\/2155620"],"URL":"https:\/\/doi.org\/10.1145\/2155620.2155655","relation":{},"subject":[],"published":{"date-parts":[[2011,12,3]]},"assertion":[{"value":"2011-12-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}