{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,3]],"date-time":"2026-10-03T18:56:18Z","timestamp":1791053778758,"version":"4.1.0"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2011,12,3]],"date-time":"2011-12-03T00:00:00Z","timestamp":1322870400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,12,3]]},"DOI":"10.1145\/2155620.2155656","type":"proceedings-article","created":{"date-parts":[[2012,3,6]],"date-time":"2012-03-06T13:18:26Z","timestamp":1331039906000},"page":"308-317","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":311,"title":["Improving GPU performance via large warps and two-level warp scheduling"],"prefix":"10.1145","author":[{"given":"Veynu","family":"Narasiman","sequence":"first","affiliation":[{"name":"The University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael","family":"Shebanow","sequence":"additional","affiliation":[{"name":"Nvidia Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chang Joo","family":"Lee","sequence":"additional","affiliation":[{"name":"Intel Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rustam","family":"Miftakhutdinov","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yale N.","family":"Patt","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2011,12,3]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Advanced Micro Devices Inc. ATI Stream Technology. http:\/\/www.amd.com\/stream.  Advanced Micro Devices Inc. ATI Stream Technology . http:\/\/www.amd.com\/stream."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325119"},{"issue":"2","key":"e_1_3_2_1_3_1","first-page":"175","volume":"35","author":"Amrutur B.","year":"2000","unstructured":"B. Amrutur and M. Horowitz . Speed and power scaling of SRAMs. IEEE JSCC , 35 ( 2 ): 175 -- 185 , Feb. 2000 . B. Amrutur and M. Horowitz. Speed and power scaling of SRAMs. IEEE JSCC, 35(2):175--185, Feb. 2000.","journal-title":"Speed and power scaling of SRAMs. IEEE JSCC"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1972.8647"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014893"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.12"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1543753.1543756"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2009.48"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10007"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360145"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106784"},{"key":"e_1_3_2_1_13_1","unstructured":"Khronos Group. OpenCL. http:\/\/www.khronos.org\/opencl.  Khronos Group. OpenCL . http:\/\/www.khronos.org\/opencl."},{"key":"e_1_3_2_1_14_1","volume-title":"Programming Massively Parallel Processors: A Hands-on Approach","author":"Kirk D.","year":"2010","unstructured":"D. Kirk and W. W. Hwu . Programming Massively Parallel Processors: A Hands-on Approach . Elsevier Science , 2010 . D. Kirk and W. W. Hwu. Programming Massively Parallel Processors: A Hands-on Approach. Elsevier Science, 2010."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006736"},{"key":"e_1_3_2_1_16_1","volume-title":"Workshop on Language, Compiler, and Architecture Support for GPGPU","author":"Lakshminarayana N. B.","year":"2010","unstructured":"N. B. Lakshminarayana and H. Kim . Effect of instruction fetch and memory scheduling on gpu performance . In Workshop on Language, Compiler, and Architecture Support for GPGPU , 2010 . N. B. Lakshminarayana and H. Kim. Effect of instruction fetch and memory scheduling on gpu performance. In Workshop on Language, Compiler, and Architecture Support for GPGPU, 2010."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815992"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2006.302743"},{"key":"e_1_3_2_1_19_1","unstructured":"NVIDIA. CUDA GPU Computing SDK. http:\/\/developer.nvidia.com\/gpu-computing-sdk.  NVIDIA. CUDA GPU Computing SDK . http:\/\/developer.nvidia.com\/gpu-computing-sdk."},{"key":"e_1_3_2_1_20_1","volume-title":"CUDA Programming Guide Version 3.0","author":"NVIDIA.","year":"2010","unstructured":"NVIDIA. CUDA Programming Guide Version 3.0 , 2010 . NVIDIA. CUDA Programming Guide Version 3.0, 2010."},{"key":"e_1_3_2_1_21_1","volume-title":"PTX ISA Version 2.0","author":"NVIDIA.","year":"2010","unstructured":"NVIDIA. PTX ISA Version 2.0 , 2010 . NVIDIA. PTX ISA Version 2.0, 2010."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/359327.359336"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1345206.1345220"},{"key":"e_1_3_2_1_24_1","volume-title":"ICPP","author":"Smith B. J.","year":"1978","unstructured":"B. J. Smith . A pipelined shared resource MIMD computer . In ICPP , 1978 . B. J. Smith. A pipelined shared resource MIMD computer. In ICPP, 1978."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339693"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1464039.1464045"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/563998.564038"}],"event":{"name":"MICRO-44: The 44th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Porto Alegre Brazil","acronym":"MICRO-44","sponsor":["IEEE","ACM Association for Computing Machinery","UFRGS Universidade Federal do Rio Grande do Sul","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS Computer Society"]},"container-title":["Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2155620.2155656","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2155620.2155656","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:07:59Z","timestamp":1750273679000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2155620.2155656"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12,3]]},"references-count":27,"alternative-id":["10.1145\/2155620.2155656","10.1145\/2155620"],"URL":"https:\/\/doi.org\/10.1145\/2155620.2155656","relation":{},"subject":[],"published":{"date-parts":[[2011,12,3]]},"assertion":[{"value":"2011-12-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}